unihd-cag / openhmc
openHMC - an open source Hybrid Memory Cube Controller
☆47Updated 8 years ago
Alternatives and similar repositories for openhmc:
Users that are interested in openhmc are comparing it to the libraries listed below
- Library defining all Ethernet packets in SystemVerilog and in SystemC☆36Updated 8 years ago
- Generic FIFO implementation with optional FWFT☆56Updated 4 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆58Updated 4 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆62Updated 8 years ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆45Updated 9 years ago
- General Purpose AXI Direct Memory Access☆48Updated 11 months ago
- Python Tool for UVM Testbench Generation☆52Updated 10 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆102Updated 3 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 4 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆28Updated this week
- ☆66Updated 2 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆64Updated 2 months ago
- ☆20Updated 5 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 4 years ago
- Repository gathering basic modules for CDC purpose☆53Updated 5 years ago
- Verilog Content Addressable Memory Module☆104Updated 3 years ago
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆57Updated 9 months ago
- amba3 apb/axi vip☆47Updated 10 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆38Updated 4 years ago
- ☆54Updated 4 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆17Updated 6 years ago
- A simple DDR3 memory controller☆54Updated 2 years ago
- SoCRocket - Core Repository☆35Updated 8 years ago
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆79Updated 5 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated 11 months ago
- Hamming ECC Encoder and Decoder to protect memories☆31Updated 2 months ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆42Updated 11 months ago
- educational microarchitectures for risc-v isa☆66Updated 6 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆83Updated 4 years ago