A collection of cryptographic algorthms implemented in SystemVerilog
☆20Jun 7, 2018Updated 8 years ago
Alternatives and similar repositories for Cryptography-in-Systemverilog
Users that are interested in Cryptography-in-Systemverilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆17Jun 5, 2024Updated 2 years ago
- ☆14May 8, 2025Updated last year
- SystemVerilog file list pruner☆19Updated this week
- JSON lib in Systemverilog☆44Feb 23, 2022Updated 4 years ago
- A straightforward (complete) sample of how to implement AES-GCM by using Linux crypto API at kernel side☆13Oct 6, 2022Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Cost Model☆20Apr 11, 2025Updated last year
- Baseband Receiver IP for GPS like DSSS signals☆43May 19, 2020Updated 6 years ago
- (elastic) cuckoo hashing☆17Jun 20, 2020Updated 6 years ago
- A fault-tolerant RDMA-based disaggregated key-value store with 1-RTT UPDATEs and GETs thanks to the SWARM replication protocol☆14Sep 25, 2024Updated last year
- Virtio implementation in SystemVerilog☆50Jan 23, 2018Updated 8 years ago
- ☆42Oct 26, 2021Updated 4 years ago
- Making cocotb testbenches that bit easier☆42Feb 28, 2026Updated 6 months ago
- This repository explores writing cocotb-style tests in modern C++, using coroutines and strong typing, with the goal of maintaining a Pyt…☆29Feb 16, 2026Updated 6 months ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55May 30, 2017Updated 9 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆12Sep 23, 2022Updated 3 years ago
- ☆15Jun 17, 2025Updated last year
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆27Updated this week
- Elgamal's over Elliptic Curves☆20Dec 22, 2018Updated 7 years ago
- Exploring Shared Virtual Memory Abstractions in OpenCL Tools for FPGAs☆18Dec 7, 2017Updated 8 years ago
- Various utilities for working with FPGAs☆13Mar 30, 2016Updated 10 years ago
- Prototype for an in memory fuzzer☆13Aug 1, 2017Updated 9 years ago
- DUA, is a communication architecture that provides uniform access for FPGA to data center resources. Without being limited by machine bou…☆40Aug 30, 2022Updated 4 years ago
- Generate UVM register model from compiled SystemRDL input☆61Nov 25, 2025Updated 9 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- SystemVerilog Design Patterns☆26Mar 11, 2015Updated 11 years ago
- This project contains Verilog designs and a PCB for the implementation of CSI-2 camera interface to HDMI bridge on a Gatemate FPGA from C…☆21Jul 28, 2025Updated last year
- Computer Graphics Metafile☆10Apr 12, 2021Updated 5 years ago
- A novel Design-for-Test flow using LibreLane☆46May 9, 2026Updated 3 months ago
- Connect to your VHDL simulation via JTAG! GDB <-TCP-> OpenOCD <-remote bitbang-> cosim_jtag <-VHPI or FLI-> VHDL simulator.☆15Dec 30, 2025Updated 8 months ago
- Overcoming the IOTLB Wall for Multi-100-Gbps Linux-based Networking☆23May 16, 2023Updated 3 years ago
- Linux kernel source tree☆12Updated this week
- Fully parametrizable combinatorial parallel LFSR/CRC module☆163Feb 27, 2025Updated last year
- Bitstream Fault Analysis Tool☆16Jul 17, 2023Updated 3 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- ☆11Sep 26, 2020Updated 5 years ago
- SHA-256 IP core for ZedBoard (Zynq SoC)☆31Jun 22, 2018Updated 8 years ago
- This Repo contains SystemC for testBench for AMBA® 3 AHB-Lite Protocol☆14Jul 11, 2018Updated 8 years ago
- SpinalHDL components for Corundum Ethernet☆15Aug 16, 2023Updated 3 years ago
- Reference HDL code for the MATRIX Creator's Spartan 6 FPGA☆28Jan 15, 2020Updated 6 years ago
- Blackwire SpinalHDL components implementing WireGuard primitives☆16Aug 16, 2023Updated 3 years ago
- 第一期安全编写指南,主要是为了提高小密圈会员群,红日小组单独成立一个项目,来提高小伙伴Python安全编写。主要涉及安全脚本开发、POC编写、安全扫描器编写。目前内容不敢涉及太多,由于小密圈基础不统一,所以我们从基础开始做起。如果你想学习,没有组织,没有团队,那么你可以加入…☆12Dec 5, 2017Updated 8 years ago