Alternatives and similar repositories for yosys-plugins:

Users that are interested in yosys-plugins are comparing it to the libraries listed below

• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated 2 years ago
• cloudxcc / Arduissimo
  Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).
  ☆21Updated 5 years ago
• knielsen / ice40_viewer
  ☆59Updated last year
• haojunliu / OpenFPGA
  OpenFPGA
  ☆33Updated 7 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated last year
• litex-hub / litehyperbus
  Small footprint and configurable HyperBus core
  ☆11Updated 2 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆39Updated 2 months ago
• ZipCPU / s6soc
  CMod-S6 SoC
  ☆40Updated 7 years ago
• mattvenn / logLUTs
  Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.
  ☆20Updated last year
• mattvenn / fpga-sram
  mystorm sram test
  ☆27Updated 7 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆62Updated 2 weeks ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago
• thotypous / alterajtaguart
  Altera JTAG UART wrapper for Bluespec
  ☆25Updated 11 years ago
• icebreaker-fpga / icebreaker-amaranth-examples
  This repository contains iCEBreaker examples for Amaranth HDL.
  ☆38Updated last year
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆86Updated 6 years ago
• GMM-7550 / gmm7550-hardware
  CologneChip GateMate FPGA Module: GMM-7550
  ☆21Updated last year
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last month
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 3 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆33Updated 8 years ago
• stevenbell / csirx
  Open-source CSI-2 receiver for Xilinx UltraScale parts
  ☆37Updated 5 years ago
• daveshah1 / flow-examples
  Misc open FPGA flow examples
  ☆8Updated 5 years ago
• projf / fpgatools
  Tools for FPGA development.
  ☆44Updated last year
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated last year
• apertus-open-source-cinema / naps
  An experiment for building gateware for the axiom micro / beta using amaranth-hdl
  ☆40Updated this week
• ArcaneNibble / KinglerPAR
  Next-Generation FPGA Place-and-Route
  ☆10Updated 6 years ago
• gtjennings1 / UPDuino-LH154Q01-Display
  Design to connect Lattice Ultraplus FPGA to LH154Q01 Display
  ☆28Updated 6 years ago
• GuzTech / ulx3s-nmigen-examples
  nMigen examples for the ULX3S board
  ☆16Updated 4 years ago
• daveshah1 / ulx3s
  ☆10Updated 6 years ago