Alternatives and similar repositories for yosys-plugins

Users that are interested in yosys-plugins are comparing it to the libraries listed below

• haojunliu / OpenFPGA
  OpenFPGA
  ☆34Updated 7 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated 2 years ago
• cliffordwolf / icotools
  Tools and Examples for IcoBoard
  ☆80Updated 4 years ago
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆91Updated 7 years ago
• projf / fpgatools
  Tools for FPGA development.
  ☆48Updated 3 months ago
• featherweight-ip / fwrisc
  Featherweight RISC-V implementation
  ☆53Updated 3 years ago
• jeanthom / gram
  DDR3 controller for nMigen (WIP)
  ☆14Updated last year
• knielsen / ice40_viewer
  ☆61Updated 2 years ago
• olofk / observer
  ☆42Updated 5 years ago
• icebreaker-fpga / icebreaker-amaranth-examples
  This repository contains iCEBreaker examples for Amaranth HDL.
  ☆39Updated 2 years ago
• litex-hub / litehyperbus
  Small footprint and configurable HyperBus core
  ☆13Updated 3 years ago
• cloudxcc / Arduissimo
  Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).
  ☆21Updated 5 years ago
• laforest / Octavo
  Verilog FPGA Parts Library. Old Octavo soft-CPU project.
  ☆75Updated 6 years ago
• daveshah1 / ulx3s
  ☆10Updated 7 years ago
• cliffordwolf / PonyLink
  A single-wire bi-directional chip-to-chip interface for FPGAs
  ☆123Updated 9 years ago
• torc-isi / torc
  Torc: Tools for Open Reconfigurable Computing
  ☆39Updated 8 years ago
• thotypous / alterajtaguart
  Altera JTAG UART wrapper for Bluespec
  ☆25Updated 11 years ago
• stevenbell / csirx
  Open-source CSI-2 receiver for Xilinx UltraScale parts
  ☆37Updated 6 years ago
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆91Updated 6 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆39Updated 4 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆34Updated 9 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• SteffenReith / J1Sc
  A reimplementation of a tiny stack CPU
  ☆85Updated last year
• rajesh-s / axi_cheatsheet
  A quick reference/ cheatsheet for the ARM AMBA Advanced eXtensible Interface (AXI)
  ☆30Updated 7 years ago
• emard / ulx3s-misc
  Miscellaneous ULX3S examples (advanced)
  ☆81Updated 4 months ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆57Updated last week
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆86Updated 5 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆68Updated 2 months ago
• TUM-LIS / glip
  Generic Logic Interfacing Project
  ☆48Updated 5 years ago