Gogireddyravikiran / Static-Timing-AnalysisView external linksLinks
Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing violations. STA breaks a design down into timing paths, calculates the signal propagation delay along each path, and checks for violations of timing constraints inside the design and at the input/output interface.
☆17Oct 4, 2022Updated 3 years ago
Alternatives and similar repositories for Static-Timing-Analysis
Users that are interested in Static-Timing-Analysis are comparing it to the libraries listed below
Sorting:
- SystemVerilog file list pruner☆16Updated this week
- GL0AM GPU Accelerated Gate Level Logic Simulator☆30Updated this week
- Open-source PDK version manager☆39Nov 25, 2025Updated 2 months ago
- Administrative repository for the Integrated Matrix Extension Task Group☆33Dec 15, 2025Updated 2 months ago
- Hardware implementation of a Fixed Point Recursive Forward and Inverse FFT algorithm☆16Mar 3, 2018Updated 7 years ago
- Source code for LEF/DEF☆11Oct 16, 2018Updated 7 years ago
- A giant Bash script that builds Linux From Scratch☆12Nov 4, 2024Updated last year
- A GUI to help users visualize the structure of a verilog HDL project☆12Jul 26, 2015Updated 10 years ago
- Introductory course into static timing analysis (STA).☆99Jul 6, 2025Updated 7 months ago
- ☆14Mar 26, 2025Updated 10 months ago
- Chameleon: A MatMul-Free TCN Accelerator for End-to-End Few-Shot and Continual Learning from Sequential Data☆25Jun 6, 2025Updated 8 months ago
- General purpose task runner☆10Nov 10, 2025Updated 3 months ago
- RTL implementation of a ray-tracing GPU☆15Dec 18, 2012Updated 13 years ago
- PULP C910, a superscalar out-of-order RISC-V core adapted from T-Head's openC910 (Alibaba Group) and integrated into the PULP ecosystem w…☆15Jun 11, 2025Updated 8 months ago
- Custom ASIC Design for SHA-256☆14Nov 22, 2025Updated 2 months ago
- ☆16Dec 25, 2024Updated last year
- Superscalar Out-of-Order NPU Design on FPGA☆11May 17, 2024Updated last year
- The purpose of the repo is to support CORE-V Wally architectural verification☆17Nov 11, 2025Updated 3 months ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆21Apr 25, 2025Updated 9 months ago
- ☆19Nov 20, 2025Updated 2 months ago
- Open-source implementations of reference Physical True Random Number Generators (TRNG or PTRNG) based on ring oscillators.☆15Oct 15, 2025Updated 4 months ago
- Wokwi-example how the display is initialised for different boards☆12Mar 13, 2023Updated 2 years ago
- This repo is "NTHU Parallel Programing" course project.☆10Dec 5, 2017Updated 8 years ago
- IHP Open source SG13G2 Tape Out on April 2025 [Testfield T586]☆13Sep 25, 2025Updated 4 months ago
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆24Updated this week
- C++ implement a simple CNN framework to train mnist data. Done!☆10Mar 29, 2022Updated 3 years ago
- 2020级课程设计DPLL算法解决SAT问题☆12Nov 3, 2021Updated 4 years ago
- Github repository of the AIStats 2024 paper: DE-HNN: An effective neural model for Circuit Netlist representation☆14Sep 3, 2025Updated 5 months ago
- Formal Verification of RISC V IM Processor☆10Mar 27, 2022Updated 3 years ago
- This is a Weather CLI application written in Rust☆11Mar 10, 2024Updated last year
- NTHU CS6135 VLSI實體設計自動化☆12Mar 12, 2022Updated 3 years ago
- An Open-Source ASIC Design Template for the SG13G2 IHP Open-PDK.☆16Updated this week
- Edge TPU object detection on Raspberry Pi with Coral USB Accelerator by integrating TensorFlow Lite C++ API and Qt/QML☆10Jun 24, 2019Updated 6 years ago
- whatever it means☆15Jan 12, 2026Updated last month
- Parametrized RTL benchmark suite☆23Feb 6, 2026Updated last week
- Debug waveforms with GDB☆28Nov 12, 2025Updated 3 months ago
- symmetric clock tree synthesis for NTV IC design☆11May 8, 2022Updated 3 years ago
- Hardware transactions library for Amaranth☆21Feb 6, 2026Updated last week
- Self-contained RTL to GDS flow for simple chip designs☆49Jan 27, 2026Updated 2 weeks ago