Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing violations. STA breaks a design down into timing paths, calculates the signal propagation delay along each path, and checks for violations of timing constraints inside the design and at the input/output interface.
☆19Oct 4, 2022Updated 3 years ago
Alternatives and similar repositories for Static-Timing-Analysis
Users that are interested in Static-Timing-Analysis are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- OpenTestability is an open-source tool for structural analysis of digital circuits, enabling computation of SCOAP metrics, Controllibilit…☆19Aug 18, 2026Updated 2 weeks ago
- Fabric generator and CAD tools graphical frontend☆18Aug 5, 2025Updated last year
- Testfield: T593☆15Apr 27, 2026Updated 4 months ago
- GL0AM GPU Accelerated Gate Level Logic Simulator☆31Feb 11, 2026Updated 6 months ago
- Chisel RTL module of a unified ray tracer datapath pipeline. Supports ray-box intersection, ray-triangle intersection, acceleration for …☆16Jul 18, 2026Updated last month
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Hack@DAC 2021☆20Jul 24, 2024Updated 2 years ago
- SystemVerilog file list pruner☆19Updated this week
- A neural network fast inference library implementing Coral Edge TPU emulator using AVX2.☆15Mar 30, 2022Updated 4 years ago
- Complete tutorial code.☆24Apr 29, 2024Updated 2 years ago
- 3D FPGA Architecture Exploration Tool☆22Jun 22, 2026Updated 2 months ago
- DLB (Deep Learning Blocks) as a part of DPU (Deep Learning Processing Unit) is a collection of synthesizable Verilog modules for deep lea…☆22Jul 30, 2026Updated last month
- A custom AI chip to be taped out soon!☆51Dec 20, 2025Updated 8 months ago
- ☆26Jul 22, 2026Updated last month
- Superscalar Out-of-Order NPU Design on FPGA☆16May 17, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- use Zybo z7-20☆17May 21, 2025Updated last year
- Debug waveforms with GDB☆33Nov 12, 2025Updated 9 months ago
- SKY130A implementatoin of the Blake2s hash algorithm☆27Dec 3, 2025Updated 9 months ago
- A GUI to help users visualize the structure of a verilog HDL project☆12Jul 26, 2015Updated 11 years ago
- Design & Implementation of Multi Clock Domain System using Verilog HDL☆13Oct 4, 2023Updated 2 years ago
- Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format☆13Feb 13, 2020Updated 6 years ago
- Library of FPGA architectures☆34Updated this week
- General purpose task runner☆12Nov 10, 2025Updated 9 months ago
- Projects and Labs for the Parallel Programming for FPGAs book☆24Dec 3, 2025Updated 9 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Github repository of the AIStats 2024 paper: DE-HNN: An effective neural model for Circuit Netlist representation☆17Sep 3, 2025Updated last year
- Custom ASIC Design for SHA-256☆14Nov 22, 2025Updated 9 months ago
- Systolic Array implementation for ASIC Course☆15Nov 26, 2023Updated 2 years ago
- Source code for LEF/DEF☆11Oct 16, 2018Updated 7 years ago
- AXI Verification using UVM Testbench☆16Oct 20, 2024Updated last year
- ☆32Updated this week
- Theia: ray graphic processing unit☆20Jul 17, 2014Updated 12 years ago
- Structured UVM Course☆76Jan 4, 2024Updated 2 years ago
- Curriculum for a university course to teach chip design using open source EDA tools☆162Oct 21, 2023Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Learn and build GPU RTL from scratch☆22Aug 1, 2025Updated last year
- ☆39Updated this week
- LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust☆42May 17, 2024Updated 2 years ago
- SPARX: An Open-Source, Automated, Programmatically Generated, Frequency-Scalable Six-Port Receiver in 130-nm CMOS☆34Updated this week
- Hardware implementation of a Fixed Point Recursive Forward and Inverse FFT algorithm☆17Mar 3, 2018Updated 8 years ago
- RTL code of some arbitration algorithm☆17Aug 25, 2019Updated 7 years ago
- Introductory course into static timing analysis (STA).☆113Jul 6, 2025Updated last year