Wren6991 / HyperRam
simple hyperram controller
☆11Updated 6 years ago
Alternatives and similar repositories for HyperRam
Users that are interested in HyperRam are comparing it to the libraries listed below
Sorting:
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆41Updated 4 years ago
- Wishbone interconnect utilities☆41Updated 3 months ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆25Updated 2 months ago
- Verilog Repository for GIT☆32Updated 4 years ago
- ULPI Link Wrapper (USB Phy Interface)☆26Updated 5 years ago
- MMC (and derivative standards) host controller☆24Updated 4 years ago
- Universal Advanced JTAG Debug Interface☆17Updated last year
- Peripheral Component Interconnect has taken Express lane long ago, going for xGbps SerDes. Now (for the first time) in opensource on the …☆11Updated last week
- Reusable Verilog 2005 components for FPGA designs☆42Updated 2 months ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- USB 1.1 Host and Function IP core☆22Updated 10 years ago
- USB Full Speed PHY☆44Updated 5 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- Minimal DVI / HDMI Framebuffer☆80Updated 4 years ago
- A CIC filter implemented in Verilog☆22Updated 9 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated last year
- JTAG DPI module for OpenRISC simulation with Verilator☆17Updated 12 years ago
- PCI bridge☆18Updated 10 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆36Updated 6 years ago
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- Master-thesis-final☆19Updated last year
- vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.☆26Updated 9 years ago
- USB -> AXI Debug Bridge☆38Updated 3 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆20Updated last year
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆60Updated 6 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆29Updated 4 months ago
- UART models for cocotb☆28Updated 2 years ago
- UART 16550 core☆36Updated 10 years ago