This project contains Verilog designs and a PCB for the implementation of CSI-2 camera interface to HDMI bridge on a Gatemate FPGA from Cologne Chip
☆21Jul 28, 2025Updated last year
Alternatives and similar repositories for MIPI-CSI-2-HDMI-Bridge
Users that are interested in MIPI-CSI-2-HDMI-Bridge are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An attempt to reverse engineer a bitstream made for an AL3-10 FPGA☆16Jan 6, 2023Updated 3 years ago
- PCIe stack written in Amaranth.☆18Apr 27, 2026Updated 5 months ago
- Openhardware educational platform based on the ideas of the ulx3s and Gecko4Education☆18Jul 16, 2025Updated last year
- Utilities for the ECP5 FPGA☆17Aug 5, 2021Updated 5 years ago
- LunaPnR is a place and router for integrated circuits☆47Feb 11, 2026Updated 8 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- HDL-first mixed-signal co-simulation: embed ngspice circuits in Verilog through VPI☆75Sep 22, 2026Updated 3 weeks ago
- Library with VHDL cores implementing Advanced Microcontroller Bus Architecture 5 (AMBA5) specifications such as APB, AHB, AXI, and AXI-St…☆18Oct 4, 2026Updated last week
- Project Peppercorn - GateMate FPGA Bitstream Documentation☆47Jun 16, 2026Updated 3 months ago
- ☆30Jul 25, 2026Updated 2 months ago
- ulx3s ghdl examples☆16Mar 6, 2021Updated 5 years ago
- WCH CH569 SerDes Reverse Engineering☆31Aug 13, 2022Updated 4 years ago
- USB Full-Speed core written in migen/LiteX☆12Sep 19, 2019Updated 7 years ago
- Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM☆52Jul 11, 2025Updated last year
- Set up your GitHub Actions workflow with a OSS CAD Suite☆18Mar 19, 2026Updated 6 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- AVR CPU Core Implementation in Verilog HDL.☆15Oct 28, 2018Updated 7 years ago
- Elements Software Development Kit☆13Jan 8, 2026Updated 9 months ago
- Open-source SystemVerilog simulator in Rust. 4-state, event-driven, IEEE 1800-2023, runs real UVM.☆95Updated this week
- Yet Another VHDL tool☆30May 15, 2017Updated 9 years ago
- ☆16Apr 24, 2025Updated last year
- Projects for the ECPiX-5 - a ECP5 FPGA board.☆15Jul 5, 2020Updated 6 years ago
- Graphical intuition to MOSFET square-law☆12Jan 5, 2021Updated 5 years ago
- 10 Gigabit Ethernet MAC Core UVM Verification☆19Oct 5, 2023Updated 3 years ago
- This repository provides an automated shell script to set up a Verilator + UVM-based workflow using the [RTL2UVM](https://github.com/rpja…☆21Oct 21, 2025Updated 11 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- cocotb extension for nMigen☆17Feb 26, 2022Updated 4 years ago
- Minimal ZX Spectrum for Ulx3s ECP5 board☆12May 7, 2020Updated 6 years ago
- ☆10May 27, 2026Updated 4 months ago
- HeiChips 2025 LibreLane Workshop☆18Aug 25, 2025Updated last year
- Ultimate ECP5 development board☆122Jul 4, 2019Updated 7 years ago
- [MIGRATED to https://codeberg.org/prjunnamed/prjcombine/] An FPGA reverse engineering and documentation project☆66Mar 12, 2026Updated 7 months ago
- HiLoTOF -- Hardware-in-the-Loop Test framework for Open FPGAs☆13Feb 9, 2019Updated 7 years ago
- Summer School Week 1 & 2 repo☆12Jul 1, 2022Updated 4 years ago
- VS Code extension for SystemVerilog design navigation, RTL tracing, schematic viewer, and waveform integration☆63Jul 25, 2026Updated 2 months ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Picorv32 SoC that uses only BRAM, not flash memory☆13Nov 27, 2018Updated 7 years ago
- [MIGRATED to https://codeberg.org/prjunnamed/prjunnamed] End-to-end synthesis and P&R toolchain☆95Mar 12, 2026Updated 7 months ago
- community projects that can be used with the ULX3S FPGA ESP32 board☆22Sep 21, 2026Updated 3 weeks ago
- An FPGA/PCI Device Reference Platform☆32Dec 10, 2020Updated 5 years ago
- Soft-logic designs and HAL libraries for various subsystems found in Oxide hardware.☆24Updated this week
- Lattice ECP5 variant of SD2SNES☆20Feb 18, 2021Updated 5 years ago
- EVEREST: e-Versatile Research Stick for peoples☆37Apr 12, 2023Updated 3 years ago