Alternatives and similar repositories for PearlRiver

Users that are interested in PearlRiver are comparing it to the libraries listed below

• leviathanch / libresiliconprocess
  ☆29Updated 5 years ago
• lowRISC / lowrisc-fpga
  Untethered (stand-alone) FPGA implementation of the lowRISC SoC
  ☆56Updated 5 years ago
• chipforge / StdCellLib
  Copyleftist's Standard Cell Library
  ☆99Updated last year
• libresilicon / process
  ☆91Updated 5 years ago
• leviathanch / qtflow
  A Qt5 based free VLSI development tool
  ☆30Updated 7 years ago
• leviathanch / SITCON
  Slides for the talk I have very soon
  ☆12Updated 6 years ago
• betrusted-io / betrusted-ec
  Betrusted embedded controller (UP5K)
  ☆46Updated last year
• libresilicon / coriolis
  autorouter forked from https://www-soc.lip6.fr/git/coriolis.git
  ☆15Updated 7 years ago
• tinyfpga / TinyFPGA-SoC
  Opensource building blocks for TinyFPGA microcontrollers and retro computers.
  ☆17Updated 7 years ago
• KestrelComputer / S64X7
  64-bit MISC Architecture CPU
  ☆12Updated 8 years ago
• trabucayre / quickfeather-notes
  Notes, scripts and apps to quickfeather board
  ☆10Updated 3 years ago
• f4pga / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
  ☆34Updated 3 years ago
• riscvarchive / riscv-lld
  RISC-V port of LLVM Linker
  ☆24Updated 6 years ago
• YoWASP / yosys
  Unofficial Yosys WebAssembly packages
  ☆71Updated this week
• libresilicon / magic-8.2
  Magic VLSI Layout Tool
  ☆21Updated 5 years ago
• onchipuis / mriscvcore
  A 32-bit RISC-V processor for mriscv project
  ☆58Updated 7 years ago
• CTSRD-CHERI / beri
  The BERI and CHERI processor and hardware platform
  ☆49Updated 8 years ago
• CTSRD-CHERI / RVBS
  RISC-V BSV Specification
  ☆20Updated 5 years ago
• JohnDRO / Golirev-IDE
  An online Verilog IDE based on YosysJS.
  ☆24Updated 9 years ago
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated 2 years ago
• Poofjunior / fpga_fast_serial_sort
  a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially
  ☆40Updated 9 years ago
• YosysHQ / yosys-plugins
  Yosys Plugins
  ☆21Updated 5 years ago
• stacksmith / fpgasm
  FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)
  ☆53Updated 3 years ago
• mballance / fwrisc-s
  ☆10Updated 5 years ago
• pepijndevos / seqpu
  A bit-serial CPU
  ☆19Updated 5 years ago
• haojunliu / OpenFPGA
  OpenFPGA
  ☆34Updated 7 years ago
• tcr / rust-verilog
  Verilog parsing and generator crate.
  ☆21Updated 5 years ago
• chipy-hdl / chipy
  chipy hdl
  ☆17Updated 7 years ago
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 3 years ago
• tommythorn / yari
  YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…
  ☆45Updated 7 months ago