fpgasystems / GPU-FPGA-Recommendation-System
FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters
☆16Updated 3 years ago
Alternatives and similar repositories for GPU-FPGA-Recommendation-System:
Users that are interested in GPU-FPGA-Recommendation-System are comparing it to the libraries listed below
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- ☆23Updated 4 years ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS☆18Updated 5 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 6 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆62Updated last year
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- ☆34Updated 3 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆86Updated 5 months ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆30Updated 3 years ago
- ☆29Updated 5 months ago
- DASS HLS Compiler☆29Updated last year
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆48Updated 7 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆38Updated 3 months ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 2 years ago
- ☆26Updated 5 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆18Updated 6 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆70Updated 3 years ago
- HLS for Networks-on-Chip☆33Updated 4 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆14Updated last year
- cycle accurate Network-on-Chip Simulator☆27Updated last year
- Centaur, a framework for hybrid CPU-FPGA databases☆27Updated 7 years ago
- ☆15Updated 2 years ago
- ☆8Updated last year
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 3 years ago
- ☆23Updated 2 years ago
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆22Updated last week