ycchen218 / EDA-DRC-PredictionLinks
This is a deep-learning based model for Electronic Design Automation(EDA), predicting the Design Rule Check (DRC) violation location.
☆12Updated 2 years ago
Alternatives and similar repositories for EDA-DRC-Prediction
Users that are interested in EDA-DRC-Prediction are comparing it to the libraries listed below
Sorting:
- This library is a low level parser for the OpenAccess file format.☆15Updated 8 years ago
- ☆26Updated 4 years ago
- This library is a low level parser for the GDSII file format.☆35Updated 8 years ago
- VLSI placement and routing tool☆15Updated last year
- ChatEDA: A Large Language Model Powered Autonomous Agent for EDA (TCAD'24, NAACL'25)☆35Updated 6 months ago
- An open multiple patterning framework☆80Updated last year
- This repo awesome-AI4EDA contains the source for the webpage: https://ai4eda.github.io, which is a curated paper list of awesome AI for E…☆172Updated 5 months ago
- ☆27Updated 6 months ago
- ☆31Updated 3 years ago
- Tapeouts done using OpenFASOC☆14Updated 3 weeks ago
- Mirror of the Si2 LEF/DEF parser (v5.8)☆17Updated 4 years ago
- GDSII manipulation libaray☆17Updated last week
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆187Updated 6 months ago
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆161Updated 7 months ago
- An analytical VLSI placer☆28Updated 4 years ago
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆146Updated 5 months ago
- A Design Rule Checker with GPU Acceleration☆58Updated 2 years ago
- ☆49Updated last year
- CUGR, VLSI Global Routing Tool Developed by CUHK☆139Updated 2 years ago
- ☆92Updated 5 months ago
- Must-read papers on Graph Neural Networks (GNNs) for Integrated Circuits (ICs) design, security and reliability.☆70Updated 4 months ago
- Analog Placement Quality Prediction☆25Updated 2 years ago
- Circuit release of the MAGICAL project☆40Updated 5 years ago
- EDA physical synthesis optimization kit☆62Updated 2 years ago
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆139Updated 2 years ago
- Optimal gate sizing of digital circuits using geometric programming☆11Updated 9 years ago
- This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024☆52Updated 10 months ago
- Library Exchange Format (LEF) and Design Exchange Format (DEF)☆23Updated 5 years ago
- GDSII File Parsing, IC Layout Analysis, and Parameter Extraction☆126Updated 2 years ago
- ChiPBench:Benchmarking End-to-End Performance of AI-based Chip Placement Algorithms☆46Updated 2 months ago