ycchen218 / EDA-DRC-PredictionLinks
This is a deep-learning based model for Electronic Design Automation(EDA), predicting the Design Rule Check (DRC) violation location.
☆12Updated 2 years ago
Alternatives and similar repositories for EDA-DRC-Prediction
Users that are interested in EDA-DRC-Prediction are comparing it to the libraries listed below
Sorting:
- This library is a low level parser for the OpenAccess file format.☆15Updated 8 years ago
- This library is a low level parser for the GDSII file format.☆35Updated 8 years ago
- VLSI placement and routing tool☆14Updated last year
- A single-script repo for a script to turn a calibre layer file to a KLayout .lyp file☆13Updated 7 years ago
- ☆24Updated 3 months ago
- ☆25Updated 4 years ago
- Tapeouts done using OpenFASOC☆11Updated last year
- GDSII manipulation libaray☆17Updated last year
- ☆31Updated 3 years ago
- This repo awesome-AI4EDA contains the source for the webpage: https://ai4eda.github.io, which is a curated paper list of awesome AI for E…☆167Updated 2 months ago
- GDS to ASCII Converter☆21Updated 2 months ago
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆136Updated 2 months ago
- ☆45Updated last year
- This is a deep-learning based model for Electronic Design Automation(EDA), predicting the IR drop location on the chip.☆28Updated 2 years ago
- SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility (DATE2023)☆21Updated 2 years ago
- LLM-Enhanced Bayesian Optimization for Efficient Analog Constraint Generation☆22Updated 10 months ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆175Updated 3 months ago
- This is a deep-learning based model for Electronic Design Automation(EDA), predicting the congestion location.☆21Updated last year
- EDA physical synthesis optimization kit☆60Updated last year
- Library Exchange Format (LEF) and Design Exchange Format (DEF)☆21Updated 5 years ago
- Datasets for EDA LLM research☆33Updated 7 months ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆137Updated 2 years ago
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆154Updated 4 months ago
- ☆90Updated 2 months ago
- Assignments of Physical Design for Nanometer ICs (Spring 2017, Prof. Yao-Wen Chang)☆42Updated 6 years ago
- ☆17Updated 11 months ago
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆137Updated 2 years ago
- ChatEDA: A Large Language Model Powered Autonomous Agent for EDA (TCAD'24, NAACL'25)☆29Updated 3 months ago
- GDSII File Parsing, IC Layout Analysis, and Parameter Extraction☆124Updated 2 years ago
- An open multiple patterning framework☆79Updated last year