Alternatives and similar repositories for Standard-Cell-Characterization

Users that are interested in Standard-Cell-Characterization are comparing it to the libraries listed below

• nickson-jose / vsdstdcelldesign
  This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…
  ☆74Updated 4 years ago
• stineje / CharLib
  Open-source repository for a standard-cell library characterizer using complete open-source tools
  ☆37Updated 2 months ago
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆51Updated 5 years ago
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆164Updated last month
• chipsalliance / uvm-verilator
  ☆99Updated 2 years ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆89Updated last year
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆37Updated 2 years ago
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆98Updated 3 months ago
• vsdip / vsdsram_sky130
  ☆43Updated 3 years ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆79Updated 4 years ago
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆97Updated 3 years ago
• parallaxsw / OpenSTA
  ☆90Updated this week
• vsdip / vsdStdCellCharacterizer_sky130
  ☆20Updated 3 years ago
• bojackchen / digital-flow
  This is a tutorial on standard digital design flow
  ☆79Updated 4 years ago
• ncsu-eda / FreePDK3
  ☆178Updated 4 years ago
• shariethernet / Physical-Design-with-OpenLANE-using-SKY130-PDK
  This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…
  ☆50Updated 4 years ago
• kunalg123 / vsdflow
  VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…
  ☆162Updated 2 years ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆166Updated this week
• The-OpenROAD-Project / megaboom
  ☆30Updated last month
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆65Updated last year
• pulp-platform / svase
  ☆32Updated 9 months ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆158Updated 2 weeks ago
• praharshapm / vsdmixedsignalflow
  This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…
  ☆44Updated 4 years ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆50Updated this week
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆127Updated last month
• hanysalah / Design-Pattern-in-SV
  This repo is created to include illustrative examples on object oriented design pattern in SV
  ☆60Updated 2 years ago
• fabianschuiki / potstill
  An open source generator for standard cell based memories.
  ☆14Updated 9 years ago
• efabless / chipignite-resources
  ☆84Updated 2 years ago
• ReuelReuben / vsdSRAM
  SRAM
  ☆22Updated 5 years ago
• ShonTaware / OpenSource_Physical_Design
  This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK
  ☆43Updated 3 years ago