spider-tronix / Standard-Cell-Characterization
Open Source tool to build liberty files and for Characterizing Standard Cells.
☆24Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for Standard-Cell-Characterization
- AMC: Asynchronous Memory Compiler☆46Updated 4 years ago
- ☆39Updated 2 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆63Updated 3 years ago
- ☆29Updated 2 months ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆63Updated 3 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆42Updated 3 years ago
- Open-source repository for a standard-cell library characterizer using complete open-source tools☆20Updated 5 months ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆33Updated last year
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆34Updated 2 years ago
- Introductory course into static timing analysis (STA).☆65Updated 2 weeks ago
- reference block design for the ASAP7nm library in Cadence Innovus☆32Updated 4 months ago
- An open source generator for standard cell based memories.☆12Updated 8 years ago
- ☆100Updated 4 months ago
- SRAM☆20Updated 4 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆73Updated 7 months ago
- Mirror of Synopsys's Liberty parser library☆18Updated 6 years ago
- Python Tool for UVM Testbench Generation☆48Updated 6 months ago
- This is a tutorial on standard digital design flow☆73Updated 3 years ago
- ☆39Updated 4 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆50Updated 2 years ago
- ☆52Updated last year
- SKY130 SRAM macros generated by SRAM 22☆9Updated 3 weeks ago
- A free standard cell library for SDDS-NCL circuits☆24Updated last year
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆28Updated 4 years ago
- An automatic clock gating utility☆43Updated 4 months ago
- YosysHQ SVA AXI Properties☆32Updated last year
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆36Updated 3 years ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆56Updated 3 years ago
- PLL Designs on Skywater 130nm MPW☆20Updated 11 months ago
- ☆36Updated 7 months ago