spider-tronix / Standard-Cell-CharacterizationLinks
Open Source tool to build liberty files and for Characterizing Standard Cells.
☆28Updated 4 years ago
Alternatives and similar repositories for Standard-Cell-Characterization
Users that are interested in Standard-Cell-Characterization are comparing it to the libraries listed below
Sorting:
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆79Updated 5 years ago
- A complete open-source design-for-testing (DFT) Solution☆179Updated 5 months ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆82Updated 4 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆56Updated 4 years ago
- Open-source repository for a standard-cell library characterizer using complete open-source tools☆46Updated 2 weeks ago
- AMC: Asynchronous Memory Compiler☆52Updated 5 years ago
- ☆114Updated 3 months ago
- Introductory course into static timing analysis (STA).☆99Updated 7 months ago
- ☆41Updated 3 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆48Updated 5 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆98Updated last year
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 3 years ago
- ☆189Updated 4 years ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆201Updated 5 years ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆45Updated 3 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆164Updated 3 months ago
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.☆167Updated last month
- This is a tutorial on standard digital design flow☆83Updated 4 years ago
- ideas and eda software for vlsi design☆51Updated this week
- A Standalone Structural Verilog Parser☆99Updated 3 years ago
- ☆20Updated 4 years ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆60Updated 2 years ago
- An automatic clock gating utility☆52Updated 9 months ago
- ☆234Updated 10 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆74Updated 3 years ago
- ☆33Updated last year
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆69Updated 2 months ago
- An open source generator for standard cell based memories.☆14Updated 9 years ago
- Functional Coverage and Constrained Randomization Extensions for Cocotb☆119Updated 4 months ago
- SystemVerilog frontend for Yosys☆196Updated this week