Parametric layout generator for digital, analog and mixed-signal integrated circuits
☆83Oct 16, 2026Updated last week
Alternatives and similar repositories for openPCells
Users that are interested in openPCells are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- pcells for various magnetic passive devices (GPL v3)☆13Sep 21, 2013Updated 13 years ago
- Arbitrary Cell Generator enables parametrized grid-free circuit layout creation☆17Jun 1, 2020Updated 6 years ago
- ☆402Sep 15, 2026Updated last month
- SPARX: An Open-Source, Automated, Programmatically Generated, Frequency-Scalable Six-Port Receiver in 130-nm CMOS☆35Oct 20, 2026Updated last week
- Instrumentation amplifier (analog IP example)☆14Aug 23, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Open-source repository for a standard-cell library characterizer using complete open-source tools☆70Sep 22, 2026Updated last month
- Interchange formats for chip design.☆40Feb 15, 2026Updated 8 months ago
- Hardware Description Library☆96Feb 17, 2026Updated 8 months ago
- ☆42Oct 16, 2026Updated last week
- Advanced Integrated Circuits 2025☆14Nov 1, 2025Updated 11 months ago
- Circuit Automatic Characterization Engine☆16Sep 24, 2026Updated last month
- A tiny Python package to parse spice raw data files.☆54Dec 26, 2022Updated 3 years ago
- Coriolis VLSI EDA Tool (LIP6)☆94Oct 18, 2026Updated last week
- Advanced Integrated Circuits 2024☆24Nov 16, 2024Updated last year
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design. Documentation is here:☆862Updated this week
- A Python and SKILL Framework for Cadence Virtuoso☆60Dec 13, 2025Updated 10 months ago
- Circuit Automatic Characterization Engine☆58Feb 7, 2025Updated last year
- Utilities for working with Cadence's SKILL/SKILL++ including a unit testing framework.☆49Nov 6, 2020Updated 5 years ago
- ☆94Nov 7, 2022Updated 3 years ago
- A simple 5-transistor OTA.☆12Jun 27, 2025Updated last year
- This repository contains a detailed description of how to generate parameterized cells using GDSFactory-based layout automation tool GLay…☆13Oct 14, 2024Updated 2 years ago
- Machine Generated Analog IC Layout☆304Apr 24, 2024Updated 2 years ago
- Cadence SKILL utilities that have boosted my productivity considerably for 10+ years.☆59Apr 9, 2026Updated 6 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- An Open-Source Full-Custom Silicon Compiler for High-Performance FPGA Fabrics☆21Aug 25, 2026Updated 2 months ago
- components and examples for creating radio ICs using the open skywater 130nm PDK☆18Nov 29, 2020Updated 5 years ago
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆48Mar 2, 2022Updated 4 years ago
- A package for converting IC layout (OASIS/GDS2) into 3D formats such as .GLB/glTF2.0, to load to the web.☆10Aug 8, 2023Updated 3 years ago
- ☆172Dec 4, 2022Updated 3 years ago
- Layout Symmetry Annotation for Analog Circuits with GraphNeural Networks☆17Apr 7, 2023Updated 3 years ago
- Open-source PDK version manager☆68Oct 21, 2026Updated last week
- An innovative Verilog-A compiler - reloaded☆53Updated this week
- SKILL Codes, PCell Creation☆23May 21, 2021Updated 5 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Python interface for Cadence Spectre☆28Feb 17, 2026Updated 8 months ago
- A case study of a continuous-time Delta-Sigma modulator including system-level simulations/design of the CT-DSM, circuit-design of the fr…☆17Sep 4, 2026Updated last month
- Python port of Prof. Boris Murmann's gm/ID Starter Kit☆58Jun 30, 2017Updated 9 years ago
- KLayoutPhotonicPCells Core Library. Functionallities to extend KLayout PCells for Photonics☆10Jan 10, 2020Updated 6 years ago
- Custom IC Design Platform☆124Updated this week
- Combination of Analog Circuit Sizing and DL.☆18Mar 24, 2023Updated 3 years ago
- Model SAR ADC with python!☆23Jul 8, 2022Updated 4 years ago