patrickschulz / openPCells
Parametric layout generator for digital, analog and mixed-signal integrated circuits
☆54Updated last week
Alternatives and similar repositories for openPCells:
Users that are interested in openPCells are comparing it to the libraries listed below
- A tiny Python package to parse spice raw data files.☆52Updated 2 years ago
- Python port of Prof. Boris Murmann's gm/ID Starter Kit☆54Updated 7 years ago
- repository for a bandgap voltage reference in SKY130 technology☆38Updated 2 years ago
- Python script for generating lookup tables for the gm/ID design methodology and much more ...☆81Updated this week
- This repo contains introduction of gm/id method and its application to some OTA design examples.☆14Updated last year
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆31Updated 3 years ago
- A python3 gm/ID starter kit☆47Updated 7 months ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC☆31Updated last year
- MOSIS MPW Test Data and SPICE Models Collections☆34Updated 5 years ago
- Sandbox for experimenting with Ngspice and open PDKs in Google Colab☆21Updated 10 months ago
- Circuit Automatic Characterization Engine☆46Updated 2 months ago
- Circuit release of the MAGICAL project☆35Updated 5 years ago
- Cadence SKILL utilities that have boosted my productivity considerably for 10+ years.☆42Updated 3 weeks ago
- Design of Analog Blocks in Skywaters 130nm meeting corners: different flavors of OTA, BandGap, LDO.☆27Updated 2 years ago
- cdsAsync: An Asynchronous QDI VLSI Toolset & Schematic Library☆25Updated 5 years ago
- Read Spectre PSF files☆60Updated 2 weeks ago
- LAYout with Gridded Objects☆27Updated 4 years ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆68Updated last year
- A 10bit SAR ADC in Sky130☆22Updated 2 years ago
- BAG framework☆26Updated 3 months ago
- BAG framework☆40Updated 8 months ago
- Verilog-A simulation models☆69Updated 3 months ago
- PLL Designs on Skywater 130nm MPW☆20Updated last year
- A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).☆31Updated 9 years ago
- MATLAB toolbox for interfacing with the Cadence Virtuoso IC Design System☆30Updated 8 years ago
- A Python and SKILL Framework for Cadence Virtuoso☆36Updated last year
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆62Updated 2 weeks ago
- Gm Id Kit with GUI to Work with Matlab Data file similar to Prof. Boris Murmann's gm/ID Starter Kit☆46Updated 4 years ago
- LAYout with Gridded Objects v2☆55Updated 2 months ago
- KLayout technology files for Skywater SKY130☆39Updated last year