Parametric layout generator for digital, analog and mixed-signal integrated circuits
☆82Jul 28, 2026Updated last month
Alternatives and similar repositories for openPCells
Users that are interested in openPCells are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- pcells for various magnetic passive devices (GPL v3)☆13Sep 21, 2013Updated 12 years ago
- Arbitrary Cell Generator enables parametrized grid-free circuit layout creation☆17Jun 1, 2020Updated 6 years ago
- Interchange formats for chip design.☆40Feb 15, 2026Updated 6 months ago
- ☆39Jul 23, 2026Updated last month
- SPARX: An Open-Source, Automated, Programmatically Generated, Frequency-Scalable Six-Port Receiver in 130-nm CMOS☆34Updated this week
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Open-source repository for a standard-cell library characterizer using complete open-source tools☆65Aug 20, 2026Updated last week
- ☆387Aug 18, 2026Updated last week
- A tiny Python package to parse spice raw data files.☆54Dec 26, 2022Updated 3 years ago
- Python interface for Cadence Spectre☆28Feb 17, 2026Updated 6 months ago
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design. Documentation is here:☆809Updated this week
- A Python and SKILL Framework for Cadence Virtuoso☆57Dec 13, 2025Updated 8 months ago
- Advanced Integrated Circuits 2024☆24Nov 16, 2024Updated last year
- repository for a bandgap voltage reference in SKY130 technology☆45Jan 20, 2023Updated 3 years ago
- ☆93Nov 7, 2022Updated 3 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Hardware Description Library☆96Feb 17, 2026Updated 6 months ago
- An Open-Source Full-Custom Silicon Compiler for High-Performance FPGA Fabrics☆18Updated this week
- Open-source PDK version manager☆59Updated this week
- This repository contains a detailed description of how to generate parameterized cells using GDSFactory-based layout automation tool GLay…☆13Oct 14, 2024Updated last year
- An innovative Verilog-A compiler - reloaded☆47Updated this week
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆45Mar 2, 2022Updated 4 years ago
- SKILL Codes, PCell Creation☆22May 21, 2021Updated 5 years ago
- A case study of a continuous-time Delta-Sigma modulator including system-level simulations/design of the CT-DSM, circuit-design of the fr…☆16Apr 14, 2026Updated 4 months ago
- components and examples for creating radio ICs using the open skywater 130nm PDK☆19Nov 29, 2020Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Intel's Analog Detailed Router☆43Jul 18, 2019Updated 7 years ago
- Custom IC Design Platform☆115Updated this week
- KLayoutPhotonicPCells Core Library. Functionallities to extend KLayout PCells for Photonics☆10Jan 10, 2020Updated 6 years ago
- my cadence/virtuoso/icfb skill functions develloped over the years☆171Jul 7, 2026Updated last month
- Layout Symmetry Annotation for Analog Circuits with GraphNeural Networks☆17Apr 7, 2023Updated 3 years ago
- Advanced Integrated Circuits 2025☆14Nov 1, 2025Updated 9 months ago
- Model SAR ADC with python!☆22Jul 8, 2022Updated 4 years ago
- Combination of Analog Circuit Sizing and DL.☆18Mar 24, 2023Updated 3 years ago
- Python port of Prof. Boris Murmann's gm/ID Starter Kit☆58Jun 30, 2017Updated 9 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy an…☆489Updated this week
- Coriolis VLSI EDA Tool (LIP6)☆93Updated this week
- COCOA: Collaborative Compendium on Analog Integrated Circuits☆29Jan 14, 2026Updated 7 months ago
- Characterizer☆39Updated this week
- Parasitic Extraction for KLayout☆46Updated this week
- Reads a Cadence techfile into KLayout and produces layer properties from it☆32Oct 22, 2023Updated 2 years ago
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆142Jul 7, 2026Updated last month