The-OpenROAD-Project / AutoCellGen
☆14Updated 4 months ago
Alternatives and similar repositories for AutoCellGen:
Users that are interested in AutoCellGen are comparing it to the libraries listed below
- Open Source Detailed Placement engine☆35Updated 5 years ago
- UCSD Detailed Router☆82Updated 4 years ago
- Power grid analysis☆19Updated 4 years ago
- ☆28Updated 3 years ago
- ☆22Updated 4 years ago
- Circuit release of the MAGICAL project☆30Updated 5 years ago
- A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).☆54Updated 2 years ago
- Macro placement tool for OpenROAD flow☆23Updated 4 years ago
- An open multiple patterning framework☆71Updated 8 months ago
- VLSI EDA Global Router☆71Updated 7 years ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆149Updated 3 weeks ago
- This library is a low level parser for the GDSII file format.☆32Updated 7 years ago
- GDSII File Parsing, IC Layout Analysis, and Parameter Extraction☆117Updated last year
- PACT: A Parallel Compact Thermal Simulator☆43Updated 5 months ago
- A Design Rule Checker with GPU Acceleration☆47Updated last year
- Routing Visualization for Physical Design☆18Updated 6 years ago
- ☆74Updated this week
- DATC RDF☆49Updated 4 years ago
- Optimal gate sizing of digital circuits using geometric programming☆10Updated 8 years ago
- ☆37Updated 9 months ago
- Open source EDA chip design flow☆49Updated 7 years ago
- Delay Calculation ToolKit☆27Updated 2 years ago
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆132Updated last year
- Material for OpenROAD Tutorial at DAC 2020☆46Updated 2 years ago
- IDEA project source files☆102Updated 2 months ago
- ☆40Updated 5 years ago
- Pin-Accessible Legalization for Mixed-Cell-Height Circuits☆26Updated 2 years ago
- ☆91Updated 5 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 4 years ago
- EDA physical synthesis optimization kit☆50Updated last year