Alternatives and similar repositories for AutoCellGen

Users that are interested in AutoCellGen are comparing it to the libraries listed below

• limbo018 / Limbo
  Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
  ☆186Updated 6 months ago
• magical-eda / UT-AnLay
  Analog Placement Quality Prediction
  ☆25Updated 2 years ago
• The-OpenROAD-Project / RePlAce
  RePlAce global placement tool
  ☆241Updated 5 years ago
• sanggido / OpenDP
  Open Source Detailed Placement engine
  ☆39Updated 5 years ago
• cuhk-eda / Xplace
  Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization
  ☆142Updated 5 months ago
• ASU-VDA-Lab / ASP-DAC24-Tutorial
  This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024
  ☆52Updated 10 months ago
• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆138Updated 2 years ago
• geziangfinn / easyPlace
  Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS
  ☆53Updated last year
• RsynTeam / rsyn-x
  Rsyn – An Extensible Physical Synthesis Framework
  ☆132Updated last year
• TimingPredict / TimingPredict
  Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)
  ☆82Updated last year
• azadnaeemi / GT3
  GT3 PDK
  ☆18Updated this week
• opendrc / opendrc
  A Design Rule Checker with GPU Acceleration
  ☆58Updated 2 years ago
• magical-eda / MAGICAL
  Machine Generated Analog IC Layout
  ☆259Updated last year
• cuhk-eda / dr-cu
  Dr. CU, VLSI Detailed Routing Tool Developed by CUHK
  ☆138Updated 2 years ago
• asyncvlsi / lefdef
  Mirror of the Si2 LEF/DEF parser (v5.8)
  ☆17Updated 4 years ago
• ABKGroup / PROBE3.0
  ☆49Updated last year
• purdue-onchip / gds2Para
  GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
  ☆126Updated 2 years ago
• cuhk-eda / ripple
  Pin-Accessible Legalization for Mixed-Cell-Height Circuits
  ☆29Updated 3 years ago
• cuhk-eda / cu-gr-2
  ☆47Updated last year
• The-OpenROAD-Project / TritonRoute
  UCSD Detailed Router
  ☆93Updated 4 years ago
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆44Updated last year
• ieee-ceda-datc / datc-rdf-Metrics4ML
  ☆31Updated 3 years ago
• recurme / Mixed-Cell-Height_legalizer
  ☆11Updated last year
• ABKGroup / MBFFClustering
  ☆13Updated last year
• geochrist / dctk
  Delay Calculation ToolKit
  ☆32Updated 3 years ago
• jkim971201 / SkyPlace
  ☆17Updated last year
• CODA-Team / AnalogGym
  ☆62Updated 3 weeks ago
• NVlabs / INSTA
  ☆89Updated 5 months ago
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆58Updated 10 months ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆93Updated last week