Alternatives and similar repositories for AutoCellGen

Users that are interested in AutoCellGen are comparing it to the libraries listed below

• opendrc / opendrc
  A Design Rule Checker with GPU Acceleration
  ☆53Updated last year
• magical-eda / UT-AnLay
  Analog Placement Quality Prediction
  ☆23Updated 2 years ago
• magical-eda / MAGICAL
  Machine Generated Analog IC Layout
  ☆243Updated last year
• ASU-VDA-Lab / ASP-DAC24-Tutorial
  This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024
  ☆52Updated 6 months ago
• The-OpenROAD-Project / RePlAce
  RePlAce global placement tool
  ☆236Updated 4 years ago
• limbo018 / Limbo
  Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
  ☆175Updated 2 months ago
• TimingPredict / TimingPredict
  Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)
  ☆76Updated 11 months ago
• OpenTimer / Parser-SPEF
  A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
  ☆56Updated 3 years ago
• cuhk-eda / ripple
  Pin-Accessible Legalization for Mixed-Cell-Height Circuits
  ☆29Updated 3 years ago
• sanggido / OpenDP
  Open Source Detailed Placement engine
  ☆38Updated 5 years ago
• purdue-onchip / gds2Para
  GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
  ☆121Updated 2 years ago
• RsynTeam / rsyn-x
  Rsyn – An Extensible Physical Synthesis Framework
  ☆127Updated last year
• ABKGroup / PlacementEssentialReadings
  ☆57Updated 4 years ago
• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆137Updated 2 years ago
• The-OpenROAD-Project / TritonRoute
  UCSD Detailed Router
  ☆90Updated 4 years ago
• recurme / Mixed-Cell-Height_legalizer
  ☆11Updated last year
• limbo018 / OpenMPL
  An open multiple patterning framework
  ☆78Updated last year
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆39Updated last year
• geochrist / dctk
  Delay Calculation ToolKit
  ☆32Updated 3 years ago
• geziangfinn / easyPlace
  Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS
  ☆44Updated 9 months ago
• cuhk-eda / Xplace
  Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization
  ☆133Updated last month
• cuhk-eda / dr-cu
  Dr. CU, VLSI Detailed Routing Tool Developed by CUHK
  ☆135Updated 2 years ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆50Updated 5 years ago
• ieee-ceda-datc / datc-rdf-Metrics4ML
  ☆31Updated 3 years ago
• ckchengucsd / SMT-based-STDCELL-Layout-Generator
  SMT-based-STDCELL-Layout-Generator
  ☆18Updated 3 years ago
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆58Updated 4 years ago
• luckyrantanplan / nthu-route
  VLSI EDA Global Router
  ☆75Updated 7 years ago
• ALIGN-analoglayout / ALIGN-public
  ☆308Updated last month
• ABKGroup / PROBE3.0
  ☆45Updated last year
• magical-eda / MAGICAL-CIRCUITS
  Circuit release of the MAGICAL project
  ☆35Updated 5 years ago