The-OpenROAD-Project / OpenLane-MPW-CILinks
☆19Updated last year
Alternatives and similar repositories for OpenLane-MPW-CI
Users that are interested in OpenLane-MPW-CI are comparing it to the libraries listed below
Sorting:
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆79Updated 5 years ago
- A complete open-source design-for-testing (DFT) Solution☆179Updated 5 months ago
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆51Updated 5 years ago
- Introductory course into static timing analysis (STA).☆99Updated 7 months ago
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆69Updated 2 months ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆28Updated 4 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆48Updated 5 years ago
- ideas and eda software for vlsi design☆51Updated last week
- Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs☆75Updated 2 months ago
- Static Timing Analysis Full Course☆63Updated 3 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆51Updated 4 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆82Updated 4 years ago
- ☆86Updated 3 years ago
- ☆45Updated 11 months ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆164Updated 2 years ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆201Updated 5 years ago
- AMC: Asynchronous Memory Compiler☆52Updated 5 years ago
- Python Tool for UVM Testbench Generation☆55Updated last year
- A Standalone Structural Verilog Parser☆99Updated 3 years ago
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.☆167Updated last month
- [WIP] Dockerize Synopsys/Cadence EDA tools☆96Updated 6 years ago
- ☆114Updated 2 months ago
- ☆189Updated 4 years ago
- ☆234Updated 10 months ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆164Updated 2 months ago
- A plugin to allow Jenkins Steps with Cadence vManager API☆10Updated 3 weeks ago
- ☆41Updated 3 years ago
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆202Updated last month
- OpenROAD users should look at this repository first for instructions on getting started☆101Updated 4 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆74Updated 3 years ago