Alternatives and similar repositories for ChiselMIPS

Users that are interested in ChiselMIPS are comparing it to the libraries listed below

• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆35Updated last year
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆49Updated 8 months ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆49Updated last year
• huang-jl / LLCL-MIPS
  LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…
  ☆36Updated 3 years ago
• Seeker0472 / ysyx-linux
  给NEMU移植Linux Kernel!
  ☆18Updated 2 months ago
• NOP-Processor / NOP-Core
  High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
  ☆81Updated last year
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆43Updated 2 years ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated 3 months ago
• cyyself / CDIM-SoC
  SoC for CQU Dual Issue Machine
  ☆12Updated 2 years ago
• OpenXiangShan / gsim
  ☆43Updated last week
• OpenXiangShan / xfuzz
  Fuzzing General-Purpose Hardware Designs with Software Fuzzers
  ☆20Updated 3 weeks ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• OpenXiangShan / Deterload
  Xiangshan deterministic workloads generator
  ☆20Updated 2 months ago
• Kumonda221-CrO3 / gitlab-runner-vivado
  Vivado in GitLab-Runner for GitLab CI/CD
  ☆10Updated 2 years ago
• zencove-thu / zencove-zoom
  Highly configurable out-of-order MIPS32 processor, capable of booting Linux.
  ☆39Updated 2 years ago
• AlwenXXD / nscscc2021
  龙芯杯21个人赛作品
  ☆35Updated 3 years ago
• cyyself / cemu
  A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …
  ☆117Updated 9 months ago
• cassuto / yamp-32
  NSCSCC 2020 - Yet Another MIPS Processor
  ☆14Updated 3 years ago
• aaronshappell / tage-predictor
  SystemVerilog implemention of the TAGE branch predictor
  ☆12Updated 4 years ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• nscscc2019ucas / nscscc2019ucas
  ☆35Updated 5 years ago
• MaZirui2001 / Zircon
  ☆27Updated 6 months ago
• FDUCSLG / ICS-2021Spring-FDU
  Introduction to Computer Systems (II), Spring 2021
  ☆51Updated 4 years ago
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• gilgamsh / GenshinCPU
  Our repository for NSCSCC
  ☆19Updated 5 months ago
• gmlayer0 / wired
  Linux-capable out-of-order superscaler multicore LoongArch32 (LA32 / LA32R) processor.
  ☆28Updated 11 months ago
• cnyangkun / nscscc2018
  nscscc2018
  ☆26Updated 6 years ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆60Updated this week
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆44Updated last year
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆62Updated 3 years ago