Alternatives and similar repositories for la-inst

Users that are interested in la-inst are comparing it to the libraries listed below

• jiegec / unofficial-loongarch-intrinsics-guide
  Unofficial LoongArch Intrinsics Guide
  ☆60Updated last month
• OpenRigil / openrigil-rtl
  Open-source RISC-V cryptographic hardware token, RTL repo
  ☆19Updated 2 years ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆61Updated 3 years ago
• jiegec / kb
  My knowledge base
  ☆67Updated 2 weeks ago
• android-la64 / docs
  ☆20Updated 2 months ago
• loongson-community / loongarch-opcodes
  LoongArch Opcodes (unofficially compiled list)
  ☆46Updated 4 months ago
• cogbt / COGBT
  Compile Optimization Guided Binary Translator (using llvm as infrastructure)
  ☆52Updated last year
• loongson / la-asm-manual
  ☆18Updated 11 months ago
• dramforever / opensbi-h
  [No longer active] A fork of OpenSBI, with software-emulated hypervisor extension support
  ☆41Updated last month
• Martins3 / Bare-Metal-Binary-Translator
  裸金属二进制翻译器的设计和实现
  ☆45Updated 6 months ago
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆45Updated last year
• dramforever / urvirt
  User-mode trap-and-emulate hypervisor for RISC-V
  ☆13Updated 3 years ago
• loongson-community / docs
  Collection of Loongson products' public documentation
  ☆79Updated last month
• cyyself / cemu
  A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …
  ☆118Updated 11 months ago
• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆23Updated 7 months ago
• cyyself / cyyrv64
  My RV64 CPU (Work in progress)
  ☆19Updated 2 years ago
• Anillc / Yuri
  A riscv emulator.
  ☆19Updated last year
• lat-opensource / lat
  ☆208Updated this week
• loongson / la-abi-specs
  ☆32Updated 4 months ago
• jiegec / cpu-micro-benchmarks
  CPU micro benchmarks
  ☆62Updated 3 months ago
• revyos / xuantie-c900-bugs
  Summary of bugs in Xuantie C9XX core design. include C906/C908/C910/C920
  ☆24Updated 3 months ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• cnrv / OSEDA
  Open-Source EDA workshop for RISC-V community
  ☆12Updated 3 years ago
• jiegec / SPECCPU2017Harmony
  Run SPEC CPU 2017 benchmark on OpenHarmony/HarmonyOS NEXT
  ☆26Updated 3 months ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆34Updated last year
• rrwhx / LA_EMU
  Loongarch Emulator
  ☆19Updated 6 months ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• gmlayer0 / wired
  Linux-capable out-of-order superscaler multicore LoongArch32 (LA32 / LA32R) processor.
  ☆31Updated last year
• comparch-security / chipyard-random-llc
  A Rocket-Chip with a Dynamically Randomized LLC
  ☆13Updated last year
• CircuitCoder / mill
  RV32I by cats
  ☆16Updated 2 years ago