MrAMS / NagiLinks
基于difftest改进的CPU敏捷开发框架(龙芯杯2024)
☆16Updated 9 months ago
Alternatives and similar repositories for Nagi
Users that are interested in Nagi are comparing it to the libraries listed below
Sorting:
- 顺序单/双发射LA32R处理器 (龙芯杯2024) A LA32R CPU in chisel☆19Updated 7 months ago
- ☆26Updated 5 months ago
- 2022龙芯杯个人赛三等奖作品☆14Updated last year
- This is an IDE for YSYX_NPC debuging☆12Updated 6 months ago
- NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.☆13Updated 2 months ago
- nscscc2024,HPU河南理工大学参赛作品,两仪处理器☆10Updated 9 months ago
- Build mini linux for your own RISC-V emulator!☆21Updated 9 months ago
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆80Updated last year
- ☆19Updated 10 months ago
- 适用于龙芯杯团队赛入门选手的应急cache模块☆27Updated last year
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆31Updated 2 months ago
- Second Prize in NSCSCC 2024. Developed by team NoAXI from Hangzhou Dianzi University.☆17Updated 9 months ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆49Updated 7 months ago
- This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…☆16Updated 8 months ago
- Mirror of https://gitee.com/loongson-edu/open-la500.git☆17Updated 5 months ago
- ☆15Updated this week
- 2024年第八届龙芯杯 LA 个人赛二等奖参赛作品☆16Updated 10 months ago
- ☆20Updated 3 weeks ago
- "aura" my super-scalar O3 cpu core☆24Updated last year
- The official website of One Student One Chip project.☆10Updated this week
- 给NEMU移植Linux Kernel!☆18Updated 3 weeks ago
- ☆17Updated 11 months ago
- 本项目已被合并至官方Chiplab中☆12Updated 5 months ago
- Unofficial guide for ysyx students applying to ShanghaiTech University☆21Updated 3 months ago
- A framework for ysyx flow☆11Updated 7 months ago
- ☆35Updated last year
- ☆66Updated 10 months ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- ☆11Updated 4 months ago
- A 32-bit 5-stage RISC-V pipeline processor core with traps, S privilege mode, virtual memory, cache, branch prediction and TLB. Powered b…☆14Updated last year