Alternatives and similar repositories for OSEDA:

Users that are interested in OSEDA are comparing it to the libraries listed below

• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆56Updated 2 years ago
• cnrv / RVWC2021-slides
  第一届 RISC-V 中国峰会的幻灯片等资料存放
  ☆37Updated 2 years ago
• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆19Updated last month
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆21Updated last year
• TianhuaTao / uCore-SMP
  A Symmetric Multiprocessing OS Kernel over RISC-V
  ☆30Updated 2 years ago
• Oyami-Srk / RISCV-GDB-Paging
  Paging Debug tool for GDB using python
  ☆13Updated 2 years ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆29Updated 2 months ago
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆18Updated 2 weeks ago
• dramforever / ixayoi
  (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog
  ☆12Updated 3 years ago
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆36Updated last year
• CircuitCoder / ChannelOS
  What if everything is a io_uring?
  ☆16Updated 2 years ago
• jiegec / kb
  My knowledge base
  ☆42Updated this week
• jiegec / cpu
  Microarchitecture diagrams of several CPUs
  ☆24Updated 2 weeks ago
• z4yx / vivado-docker
  Dockerfile with Vivado for CI
  ☆28Updated 4 years ago
• oscomp / proj23-lightweight-hypervisor
  在RISC-V处理器上实现一个轻量级的Hypervisor。
  ☆12Updated 4 years ago
• CTSRD-CHERI / SIMTight
  Synthesisable SIMT-style RISC-V GPGPU
  ☆30Updated this week
• jiegec / verilog-lang
  A hand-written recursive decent Verilog parser.
  ☆11Updated 2 years ago
• chipsalliance / rocket-chip-blocks
  RTL blocks compatible with the Rocket Chip Generator
  ☆14Updated 7 months ago
• chipsalliance / rocket-chip-fpga-shells
  Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards
  ☆16Updated 2 months ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆30Updated 10 months ago
• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated last year
• cyyself / cpu232
  The MIPS CPU from previous CQU NSCSCC team and debugged by me running uCore MIPS porting successfully
  ☆9Updated 4 years ago
• sequencer / zaozi
  The experimental work to rewrite Chisel in pure Scala 3 and the Panama Project
  ☆23Updated this week
• jiegec / la-inst
  Examine and discover LoongArch instructions
  ☆14Updated last year
• nju-mips / noop-lo
  A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
  ☆26Updated 5 years ago
• shinezyy / gem5-official-old
  ☆16Updated 3 years ago
• jiegec / cpu-micro-benchmarks
  CPU micro benchmarks
  ☆45Updated 2 weeks ago
• xen0n / larva
  PoC LoongArch - RISC-V emulator
  ☆32Updated last year
• chyyuu / zCore-Design
  ☆13Updated 3 years ago
• redpanda3 / chisel-book
  Hardware design with Chisel
  ☆31Updated 2 years ago