Alternatives and similar repositories for JieLabs-Web:

Users that are interested in JieLabs-Web are comparing it to the libraries listed below

• jiegec / naiverouter
  A router IP written in Verilog.
  ☆13Updated 5 years ago
• jiegec / verilog-lang
  A hand-written recursive decent Verilog parser.
  ☆11Updated 2 years ago
• jiegec / Projects
  A summarize of my projects.
  ☆47Updated 9 months ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆57Updated 3 years ago
• Harry-Chen / TrivialTomasulo
  Tomasulo Simulator written in React as the project for Computer Architecture course, Spring 2019, Tsinghua University
  ☆11Updated 5 years ago
• jiegec / cpu
  Microarchitecture diagrams of several CPUs
  ☆24Updated last month
• dramforever / urvirt
  User-mode trap-and-emulate hypervisor for RISC-V
  ☆13Updated 3 years ago
• thu-cs-lab / thinpad_top
  Project template for Artix-7 based Thinpad board
  ☆45Updated last year
• char-fish-after-lunch / SystemOnCat
  An SoC with multiple RISC-V IMA processors.
  ☆19Updated 6 years ago
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆12Updated 11 months ago
• wangrunji0408 / rjrouter
  [AFK] Hardware router in Chisel (THU Network Joint Lab 2020)
  ☆14Updated 4 years ago
• meow-chip / MeowRouter
  A hardware accelerated IP packet forwarder running on programmable ICs
  ☆16Updated 2 years ago
• dramforever / ixayoi
  (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog
  ☆12Updated 3 years ago
• CircuitCoder / mill
  RV32I by cats
  ☆17Updated last year
• LyricZhao / ThinRouter
  A SystemVerilog implementation of MIPS32 CPU and RIP router
  ☆21Updated 5 years ago
• DeathWish5 / rCore_tutorial_tests
  rCore_tutorial_tests
  ☆10Updated 3 years ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated last year
• thu-cs-lab / tanlabs
  Tsinghua Advanced Networking Labs on FPGA
  ☆38Updated 4 months ago
• jiegec / kb
  My knowledge base
  ☆45Updated this week
• typekernel / typekernel
  Warning: 🕳 ahead!
  ☆16Updated 5 years ago
• CircuitCoder / ChannelOS
  What if everything is a io_uring?
  ☆16Updated 2 years ago
• jiegec / verilog-format
  A naive verilog/systemverilog formatter
  ☆20Updated 2 years ago
• twd2 / roload
  My DAC '21 work open-sourced.
  ☆14Updated 4 years ago
• Harry-Chen / HERMES
  HERMES: sHallow dirEctory stRucture Many-filE fileSystem
  ☆20Updated 5 years ago
• TrivialCompiler / Talk
  Tex source for talk slide.
  ☆10Updated 4 years ago
• thu-cs-lab / Digital-Design-Docs
  Documentation for Digital Design course
  ☆19Updated last week
• Oyami-Srk / RISCV-GDB-Paging
  Paging Debug tool for GDB using python
  ☆13Updated 2 years ago
• CircuitCoder / MeowRust
  Relaxed Rust (for cats)
  ☆16Updated 5 years ago
• z4yx / supervisor-mips32
  计算机组成原理课程32位监控程序
  ☆48Updated 4 years ago
• oscomp / proj23-lightweight-hypervisor
  在RISC-V处理器上实现一个轻量级的Hypervisor。
  ☆12Updated 4 years ago