Alternatives and similar repositories for JieLabs-Web

Users that are interested in JieLabs-Web are comparing it to the libraries listed below

• jiegec / Projects
  A summary of my projects
  ☆49Updated 2 months ago
• char-fish-after-lunch / SystemOnCat
  An SoC with multiple RISC-V IMA processors.
  ☆19Updated 6 years ago
• thu-cs-lab / thinpad_top
  Project template for Artix-7 based Thinpad board
  ☆46Updated 2 years ago
• Harry-Chen / TrivialTomasulo
  Tomasulo Simulator written in React as the project for Computer Architecture course, Spring 2019, Tsinghua University
  ☆11Updated 5 years ago
• jiegec / naiverouter
  A router IP written in Verilog.
  ☆13Updated 5 years ago
• jiegec / verilog-lang
  A hand-written recursive decent Verilog parser.
  ☆11Updated 2 years ago
• typekernel / typekernel
  Warning: 🕳 ahead!
  ☆16Updated 5 years ago
• wangrunji0408 / rjrouter
  [AFK] Hardware router in Chisel (THU Network Joint Lab 2020)
  ☆14Updated 4 years ago
• jiegec / verilog-format
  A naive verilog/systemverilog formatter
  ☆21Updated 2 months ago
• LyricZhao / ThinRouter
  A SystemVerilog implementation of MIPS32 CPU and RIP router
  ☆23Updated 5 years ago
• CircuitCoder / ChannelOS
  What if everything is a io_uring?
  ☆16Updated 2 years ago
• twd2 / roload
  My DAC '21 work open-sourced.
  ☆14Updated 4 years ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆12Updated last year
• meow-chip / MeowRouter
  A hardware accelerated IP packet forwarder running on programmable ICs
  ☆16Updated 2 years ago
• TrivialCompiler / Talk
  Tex source for talk slide.
  ☆10Updated 4 years ago
• dramforever / urvirt
  User-mode trap-and-emulate hypervisor for RISC-V
  ☆13Updated 3 years ago
• thu-cs-lab / tanlabs
  Tsinghua Advanced Networking Labs on FPGA
  ☆38Updated 7 months ago
• oscomp / proj23-lightweight-hypervisor
  在RISC-V处理器上实现一个轻量级的Hypervisor。
  ☆12Updated 4 years ago
• MashPlant / decaf-rs
  Framework of pa code for THU compiler principle course.
  ☆13Updated 5 years ago
• thu-cs-lab / Digital-Design-Docs
  Documentation for Digital Design course
  ☆20Updated 2 months ago
• CircuitCoder / mill
  RV32I by cats
  ☆16Updated last year
• Harry-Chen / HERMES
  HERMES: sHallow dirEctory stRucture Many-filE fileSystem
  ☆20Updated 5 years ago
• Oyami-Srk / RISCV-GDB-Paging
  Paging Debug tool for GDB using python
  ☆13Updated 2 years ago
• jiegec / kb
  My knowledge base
  ☆53Updated this week
• thu-cs-lab / verilog-coding-standard
  Recommended coding standard of Verilog and SystemVerilog.
  ☆34Updated 3 years ago
• DeathWish5 / rCore_tutorial_tests
  rCore_tutorial_tests
  ☆11Updated 3 years ago
• z4yx / supervisor-mips32
  计算机组成原理课程32位监控程序
  ☆48Updated 5 years ago
• cnyangkun / nscscc2017
  National Student Computer System Capability Challenge
  ☆9Updated 6 years ago
• trivialmips / TrivialMIPS_Software
  Baremetal softwares for TrivialMIPS platform
  ☆11Updated 5 years ago