OSCPU / ysyx-workbench
☆148Updated 2 weeks ago
Alternatives and similar repositories for ysyx-workbench:
Users that are interested in ysyx-workbench are comparing it to the libraries listed below
- 体系结构研讨 + ysyx高阶大纲 (WIP☆155Updated 6 months ago
- NJU Virtual Board☆274Updated 2 weeks ago
- ☆66Updated 9 months ago
- ☆63Updated 2 weeks ago
- ☆86Updated this week
- 一生一芯的信息发布和内容网站☆131Updated last year
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆132Updated 10 months ago
- 龙芯杯个人赛工具包(适用于个人赛的golden_trace工具)☆52Updated last year
- ☆36Updated last year
- verilog module add prefix script 可用于ysyx项目添加学号☆13Updated last year
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆172Updated 3 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆50Updated 2 years ago
- Modern co-simulation framework for RISC-V CPUs☆142Updated this week
- 一生一芯 , ysyx , npc . the repo of the YSYX project . a riscv-64 CPU . writing .☆28Updated 2 years ago
- 2022年龙芯杯个人赛 单发射110M(含icache)☆45Updated 2 years ago
- NSCSCC 信息整合☆240Updated 4 years ago
- An exquisite superscalar RV32GC processor.☆156Updated 3 months ago
- ☆64Updated 2 years ago
- 为了更好地帮助后来的同学参加龙芯杯,草拟了这份建议,望对后来人有所帮助☆126Updated 4 years ago
- How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design☆561Updated 8 months ago
- AXI协议规范中文翻译版☆146Updated 2 years ago
- A RISC-V RV32I ISA Single Cycle CPU☆23Updated last year
- This is my graduation project, a simple processor soft core, which implements RV32I ISA.☆17Updated 5 years ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆194Updated last month
- ☆21Updated last year
- 一生一芯CPU/目前做到cache/后续主要考虑ASIC DV☆19Updated 3 months ago
- ☆24Updated last month
- A small SoC with a pipeline 32-bit RISC-V CPU.☆63Updated 2 years ago
- ☆187Updated 3 weeks ago
- ☆162Updated last year