Alternatives and similar repositories for ysyx-workbench

Users that are interested in ysyx-workbench are comparing it to the libraries listed below

• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆172Updated 8 months ago
• NJU-ProjectN / nvboard
  NJU Virtual Board
  ☆283Updated last week
• ysyx-ta / ysyx-summer-readings
  ☆66Updated 11 months ago
• OSCPU / ysyx
  一生一芯的信息发布和内容网站
  ☆131Updated last year
• OSCPU / ysyxSoC
  ☆86Updated 2 months ago
• fluctlight001 / nscscc2022_single_tools
  龙芯杯个人赛工具包（适用于个人赛的golden_trace工具）
  ☆56Updated last year
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆138Updated last year
• OSCPU / yosys-sta
  ☆73Updated 2 months ago
• USTC-System-Courses / CECS-Lab
  ☆38Updated last year
• DawnCarol / DawnCarol
  ☆196Updated 3 months ago
• shinezyy / micro-arch-training
  How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design
  ☆582Updated 11 months ago
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆29Updated 2 years ago
• LoveLonelyTime / Bergamot
  An exquisite superscalar RV32GC processor.
  ☆159Updated 6 months ago
• MrAMS / verilogModuleAddPrefix
  verilog module add prefix script 可用于ysyx项目添加学号
  ☆13Updated last year
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆147Updated this week
• MaxXSoft / Fuxi
  Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
  ☆173Updated 4 years ago
• fluctlight001 / cpu_for_nscscc2020
  2020龙芯杯个人赛 简易双发射60M（含ibuffer）
  ☆35Updated 4 years ago
• fluctlight001 / Generic-Cache-Module
  适用于龙芯杯团队赛入门选手的应急cache模块
  ☆28Updated last year
• Yawei-Ding / ysyx_riscv64_cpu
  ☆68Updated 2 years ago
• loongson-education / nscscc-wiki
  NSCSCC 信息整合
  ☆249Updated 4 years ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• Groupsun / riscv-mini-five-stage
  This is my graduation project, a simple processor soft core, which implements RV32I ISA.
  ☆17Updated 6 years ago
• fluctlight001 / cpu_for_nscscc2022_single
  2022年龙芯杯个人赛 单发射110M（含icache）
  ☆45Updated 2 years ago
• Silverster98 / bit_nscscc_suggestion
  为了更好地帮助后来的同学参加龙芯杯，草拟了这份建议，望对后来人有所帮助
  ☆126Updated 4 years ago
• github-3rr0r / RV32ISC
  A RISC-V RV32I ISA Single Cycle CPU
  ☆24Updated last month
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 2 years ago
• ysyx-ta / ysyx-slides
  ☆30Updated 3 weeks ago
• ISRC-CAS / riscv-isa-manual-cn
  ☆177Updated last year
• Clo91eaf / PUA-MIPS
  NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.
  ☆13Updated 3 months ago
• XS-MLVP / env-xs-ov-00-bpu
  香山微架构开放验证第一期：昆明湖BPU模块UT测试模块及环境
  ☆29Updated 8 months ago