☆165Feb 22, 2026Updated last week
Alternatives and similar repositories for ysyx-workbench
Users that are interested in ysyx-workbench are comparing it to the libraries listed below
Sorting:
- NJU Virtual Board☆300Sep 5, 2025Updated 5 months ago
- ☆93Sep 30, 2025Updated 5 months ago
- The official website of One Student One Chip project.☆11Feb 5, 2026Updated 3 weeks ago
- This is an IDE for YSYX_NPC debuging☆12Dec 10, 2024Updated last year
- Modern co-simulation framework for RISC-V CPUs☆171Feb 20, 2026Updated last week
- How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design☆626Aug 13, 2024Updated last year
- ☆21May 26, 2025Updated 9 months ago
- 给NEMU移植Linux Kernel!☆22Jun 1, 2025Updated 9 months ago
- ☆71Feb 2, 2026Updated last month
- Basic chisel difftest environment for RTL design (WIP☆20Mar 8, 2025Updated 11 months ago
- ☆104Nov 17, 2025Updated 3 months ago
- ☆11Dec 23, 2025Updated 2 months ago
- 一生一芯的信息发布和内容网站☆136Nov 21, 2023Updated 2 years ago
- ☆19May 1, 2023Updated 2 years ago
- XiangShan Frontend Develop Environment☆68Updated this week
- A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …☆119Oct 31, 2024Updated last year
- ☆36Jul 22, 2025Updated 7 months ago
- Unofficial guide for ysyx students applying to ShanghaiTech University☆23Feb 25, 2025Updated last year
- 体系结构研讨 + ysyx高阶大纲 (WIP☆199Oct 14, 2024Updated last year
- ☆14Jul 23, 2025Updated 7 months ago
- ☆32Oct 21, 2025Updated 4 months ago
- ☆93Nov 12, 2025Updated 3 months ago
- Super fast RISC-V ISA emulator for XiangShan processor☆311Updated this week
- ☆66Aug 5, 2024Updated last year
- RISC-V SoC designed by students in UCAS☆1,508Jan 14, 2026Updated last month
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆32Apr 13, 2025Updated 10 months ago
- A RISC-V ELF psABI Document☆832Feb 6, 2026Updated 3 weeks ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆51Dec 18, 2025Updated 2 months ago
- NJU EMUlator, a full system x86/mips32/riscv32/riscv64 emulator for teaching☆1,091Nov 14, 2025Updated 3 months ago
- The Scala parser to parse riscv/riscv-opcodes generate☆24Jan 21, 2026Updated last month
- Xiangshan deterministic workloads generator☆24May 14, 2025Updated 9 months ago
- Simple RISC-V 3-stage Pipeline in Chisel☆604Aug 9, 2024Updated last year
- A minimal, modularized, and machine-independent hardware abstraction layer☆525Dec 23, 2025Updated 2 months ago
- 快速陷入处理☆39Jan 22, 2026Updated last month
- Open-source high-performance RISC-V processor☆6,875Updated this week
- Mirror of https://gitee.com/loongson-edu/open-la500.git☆26Jan 2, 2025Updated last year
- ☆22Nov 3, 2025Updated 4 months ago
- ☆22Nov 25, 2023Updated 2 years ago
- VSH(SHell for Visualizing vcd file)项目为数字波形文件命令行查看器。☆25Dec 8, 2025Updated 2 months ago