jensen-yan / kisscpuLinks
国科大一生一芯第二期: RISCV-64 五级流水线CPU
☆18Updated 4 years ago
Alternatives and similar repositories for kisscpu
Users that are interested in kisscpu are comparing it to the libraries listed below
Sorting:
- 一生一芯的信息发布和内容网站☆136Updated 2 years ago
- 一生一芯 , ysyx , npc . the repo of the YSYX project . a riscv-64 CPU . writing .☆33Updated 3 years ago
- 中国科学院大学高级计算机体系结构课程作业:使用OpenROAD-flow完成RTL到GDS全流程☆29Updated 5 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Updated 3 years ago
- 中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session☆32Updated 8 years ago
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆182Updated 4 years ago
- ☆91Updated 3 months ago
- Introduction to Computer Systems (II), Spring 2021☆52Updated 4 years ago
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆146Updated last year
- 体系结构研讨 + ysyx高阶大纲 (WIP☆193Updated last year
- ☆72Updated 2 years ago
- "aura" my super-scalar O3 cpu core☆24Updated last year
- MIT6.175 & MIT6.375 Study Notes☆45Updated 2 years ago
- ☆67Updated last year
- 体系结构课程实验:RISC-V 32I 流水线 CPU,实现37条指令,转发,冒险检测,Cache,分支预测器☆86Updated 6 years ago
- ☆160Updated 3 weeks ago
- all kind of notes, I maybe sort this in the future☆13Updated 4 months ago
- ☆40Updated 2 years ago
- ☆125Updated 3 years ago
- Pick your favorite language to verify your chip.☆75Updated last week
- ☆89Updated last month
- An out-of-order execution algorithm for pipeline CPU, implemented by verilog☆42Updated 7 years ago
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆53Updated 5 years ago
- A small SoC with a pipeline 32-bit RISC-V CPU.☆66Updated 3 years ago
- ☆19Updated 2 years ago
- A RISC-V RV32I ISA Single Cycle CPU☆25Updated 7 months ago
- nscscc2018☆27Updated 7 years ago
- 通过issue和README来记录日常学习研究笔记 关注 机器学习系统,深度学习, LLVM,性能剖视, Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using …☆78Updated 5 years ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆218Updated last month
- A simple RISC-V CPU written in Verilog.☆69Updated last year