A summary of my projects
☆49Dec 29, 2025Updated 2 months ago
Alternatives and similar repositories for Projects
Users that are interested in Projects are comparing it to the libraries listed below
Sorting:
- A collection of my undergraduate projects☆92Jul 2, 2024Updated last year
- RV32I by cats☆15Sep 4, 2023Updated 2 years ago
- Backend & Frontend for JieLabs☆22Mar 3, 2023Updated 3 years ago
- Warning: 🕳 ahead!☆16Jan 8, 2020Updated 6 years ago
- Booting multi-processors on x86 bare-metal.☆12Feb 25, 2022Updated 4 years ago
- 网络学堂 PC 端 App☆21Mar 12, 2026Updated last week
- Tomasulo Simulator written in React as the project for Computer Architecture course, Spring 2019, Tsinghua University☆11Jun 9, 2019Updated 6 years ago
- A naive verilog/systemverilog formatter☆21Mar 22, 2025Updated 11 months ago
- A router IP written in Verilog.☆12Dec 20, 2019Updated 6 years ago
- The MiniDecaf compilers.☆67Jan 16, 2021Updated 5 years ago
- A simple USB to UART board designed with KiCad.☆14May 4, 2023Updated 2 years ago
- HERMES: sHallow dirEctory stRucture Many-filE fileSystem☆20Jun 9, 2019Updated 6 years ago
- Project template for Artix-7 based Thinpad board☆52Sep 13, 2025Updated 6 months ago
- A hardware accelerated IP packet forwarder running on programmable ICs☆15Jan 21, 2023Updated 3 years ago
- 📚 The 2nd homework of the Artificial Intelligence Introduction.☆11Apr 10, 2018Updated 7 years ago
- Asynchronous OS kernel written in Rust.☆32Nov 27, 2020Updated 5 years ago
- 在线图书借阅系统 - 2017 THU OOP课大作业☆13Jul 1, 2018Updated 7 years ago
- Personal course notes (in Chinese) for THU CST.☆13Jun 23, 2018Updated 7 years ago
- [AFK] Hardware router in Chisel (THU Network Joint Lab 2020)☆14Oct 8, 2020Updated 5 years ago
- What if everything is a io_uring?☆17Nov 10, 2022Updated 3 years ago
- 计算机组成原理课程 RISC-V 监控程序，支持 32 位和 64 位☆127Dec 4, 2025Updated 3 months ago
- ☆22Nov 27, 2021Updated 4 years ago
- THU compiler principle course homework, written in rust. (this is not the pa framework)☆13Dec 24, 2018Updated 7 years ago
- Various data structures implementation, in STL style☆11Jul 26, 2021Updated 4 years ago
- rCore_tutorial_tests☆11Aug 8, 2021Updated 4 years ago
- The Decaf compiler, written in Rust☆57Dec 18, 2019Updated 6 years ago
- Tutorial for rCore OS step by step (2nd edition)☆141Dec 4, 2022Updated 3 years ago
- Implementation of several grid routers in Rust☆13Feb 28, 2026Updated 2 weeks ago
- Pinyin IME with rust - 拼音输入法rust版☆47Jun 6, 2022Updated 3 years ago
- An implementation of "Efficient Gradient-Domain Compositing Using Quadtrees", SIGGRAPH 2007.☆25Jan 9, 2020Updated 6 years ago
- Facts of DCST of Tsinghua University☆60Apr 23, 2025Updated 10 months ago
- CypherSmith is a random cypher generator for OpenCypher☆17Jan 24, 2022Updated 4 years ago
- My knowledge base☆80Mar 14, 2026Updated last week
- Rebuilding ...☆11Apr 20, 2021Updated 4 years ago
- An SoC with multiple RISC-V IMA processors.☆19Aug 1, 2018Updated 7 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Feb 17, 2022Updated 4 years ago
- Course homework & project for compiler-train-19.☆20Jan 6, 2020Updated 6 years ago
- 计算机组成原理课程32位监控程序☆50Jun 2, 2020Updated 5 years ago
- My DAC '21 work open-sourced.☆14Feb 25, 2021Updated 5 years ago