Alternatives and similar repositories for rjrouter:

Users that are interested in rjrouter are comparing it to the libraries listed below

• oscomp / proj23-lightweight-hypervisor
  在RISC-V处理器上实现一个轻量级的Hypervisor。
  ☆12Updated 4 years ago
• HUST-OS / design-pattern-notes
  各类内核的设计思路
  ☆19Updated 3 years ago
• oscomp / proj6-user-level-interrupt
  基于FPGA实现用户态中断硬件机制与优化操作系统内核
  ☆9Updated last year
• DeathWish5 / rCore_tutorial_tests
  rCore_tutorial_tests
  ☆10Updated 3 years ago
• CircuitCoder / ChannelOS
  What if everything is a io_uring?
  ☆16Updated 2 years ago
• MashPlant / decaf-rs
  Framework of pa code for THU compiler principle course.
  ☆13Updated 5 years ago
• yhtzd / skyloft
  Skyloft: A General High-Efficient Scheduling Framework in User Space (SOSP 2024)
  ☆32Updated 4 months ago
• TianhuaTao / uCore-SMP
  A Symmetric Multiprocessing OS Kernel over RISC-V
  ☆30Updated 2 years ago
• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated last year
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆21Updated last year
• axbryd / warp-artifacts
  Artifacts for ATC '22 paper "Faster Software Packet Processing on FPGA NICs with eBPF Program Warping"
  ☆17Updated 2 years ago
• were / bfsh
  Being a full-stack hacker, RISCV, LLVM, and more.
  ☆18Updated 3 years ago
• rcore-os / nvme_driver
  ☆30Updated last year
• pku-minic / first-step-rs
  Take your first step in writing a compiler. Implemented in Rust.
  ☆15Updated last year
• riscv / riscv-spmp
  The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by…
  ☆12Updated 4 months ago
• chyyuu / zCore-Design
  ☆13Updated 3 years ago
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆12Updated 10 months ago
• Oyami-Srk / RISCV-GDB-Paging
  Paging Debug tool for GDB using python
  ☆13Updated 2 years ago
• jiegec / naiverouter
  A router IP written in Verilog.
  ☆13Updated 5 years ago
• oscomp / proj4-xv6-rust
  用Rust语言重新设计与实现xv6
  ☆35Updated 2 years ago
• oscomp / proj1-rustsbi
  实现和扩展RISC-V SBI运行时，使之能够支持并运行操作系统
  ☆14Updated 2 years ago
• WukLab / FPGA-OS
  ☆33Updated 4 years ago
• Harry-Chen / TrivialTomasulo
  Tomasulo Simulator written in React as the project for Computer Architecture course, Spring 2019, Tsinghua University
  ☆11Updated 5 years ago
• char-fish-after-lunch / SystemOnCat
  An SoC with multiple RISC-V IMA processors.
  ☆19Updated 6 years ago
• OS-F-4 / usr-intr
  项目的主仓库
  ☆23Updated 2 years ago
• jiegec / verilog-lang
  A hand-written recursive decent Verilog parser.
  ☆11Updated 2 years ago
• js2xxx / umi
  An RISC-V experimental OS
  ☆25Updated last year
• TrivialCompiler / Talk
  Tex source for talk slide.
  ☆10Updated 4 years ago
• luojia65 / zihai
  自嗨虚拟化软件 - 'Enjoy yourself' type-1 hypervisor software
  ☆25Updated 2 years ago
• jiegec / kb
  My knowledge base
  ☆42Updated this week