Alternatives and similar repositories for Digital-Design-Docs

Users that are interested in Digital-Design-Docs are comparing it to the libraries listed below

• ustb-owl / Uranus
  Uranus MIPS processor by MaxXing & USTB NSCSCC team
  ☆38Updated 5 years ago
• huang-jl / LLCL-MIPS
  LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…
  ☆36Updated 3 years ago
• cnyangkun / nscscc2018
  nscscc2018
  ☆26Updated 6 years ago
• YAVGroup / Verilog-OJ
  Online judge server for Verilog | verilogoj.ustc.edu.cn
  ☆80Updated last year
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆62Updated 3 years ago
• cyyself / cpu232
  The MIPS CPU from previous CQU NSCSCC team and debugged by me running uCore MIPS porting successfully
  ☆9Updated 4 years ago
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆35Updated last year
• FDUCSLG / ICS-2021Spring-FDU
  Introduction to Computer Systems (II), Spring 2021
  ☆51Updated 4 years ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 8 months ago
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆44Updated last year
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆49Updated last year
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆12Updated last year
• cnrv / RVWC2021-slides
  第一届 RISC-V 中国峰会的幻灯片等资料存放
  ☆38Updated 2 years ago
• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated 2 years ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆49Updated 9 months ago
• RickyTino / MangoMIPS32
  A softcore microprocessor of MIPS32 architecture.
  ☆40Updated last year
• cyyself / CDIM-SoC
  SoC for CQU Dual Issue Machine
  ☆12Updated 2 years ago
• NOP-Processor / NOP-Core
  High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
  ☆81Updated last year
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• nscscc2019ucas / nscscc2019ucas
  ☆35Updated 5 years ago
• cyyself / cyyrv64
  My RV64 CPU (Work in progress)
  ☆19Updated 2 years ago
• OSCPU / ysyx
  一生一芯的信息发布和内容网站
  ☆132Updated last year
• AlwenXXD / nscscc2021
  龙芯杯21个人赛作品
  ☆35Updated 3 years ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• zencove-thu / zencove-zoom
  Highly configurable out-of-order MIPS32 processor, capable of booting Linux.
  ☆39Updated 2 years ago
• LeiWang1999 / Pynq-Accelerator
  A easy general acc.
  ☆16Updated 4 years ago
• chipsalliance / playground
  chipyard in mill :P
  ☆78Updated last year
• howardlau1999 / yatcpu
  Yet another toy CPU.
  ☆91Updated last year
• pku-liang / Hestia
  ☆17Updated 4 months ago
• jiegec / kb
  My knowledge base
  ☆63Updated this week