thu-cs-lab / Digital-Design-DocsLinks
Documentation for Digital Design course
☆20Updated 3 months ago
Alternatives and similar repositories for Digital-Design-Docs
Users that are interested in Digital-Design-Docs are comparing it to the libraries listed below
Sorting:
- Backend & Frontend for JieLabs☆22Updated 2 years ago
- LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. (第五届龙芯杯特等奖作…☆36Updated 3 years ago
- Project template for Artix-7 based Thinpad board☆46Updated 2 years ago
- The 'missing header' for Chisel☆20Updated 2 months ago
- My knowledge base☆53Updated this week
- Recommended coding standard of Verilog and SystemVerilog.☆34Updated 3 years ago
- My RV64 CPU (Work in progress)☆19Updated 2 years ago
- Lower chisel memories to SRAM macros☆12Updated last year
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆62Updated 3 years ago
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆39Updated last year
- nscscc2018☆26Updated 6 years ago
- Run Rocket Chip on VCU128☆30Updated 6 months ago
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆28Updated 5 years ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆49Updated 7 months ago
- ☆34Updated 5 years ago
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆42Updated 10 months ago
- ☆33Updated 2 months ago
- Hardware design with Chisel☆32Updated 2 years ago
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- Online judge server for Verilog | verilogoj.ustc.edu.cn☆80Updated 11 months ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- CQU Dual Issue Machine☆36Updated 11 months ago
- A router IP written in Verilog.☆13Updated 5 years ago
- The MIPS CPU from previous CQU NSCSCC team and debugged by me running uCore MIPS porting successfully☆9Updated 4 years ago
- SoC for CQU Dual Issue Machine☆12Updated 2 years ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆48Updated last year
- A softcore microprocessor of MIPS32 architecture.☆39Updated 11 months ago
- 第一届 RISC-V 中国峰会的幻灯片等资料存放☆37Updated 2 years ago
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆80Updated last year
- ☆14Updated 2 months ago