thu-cs-lab / Digital-Design-DocsLinks
Documentation for Digital Design course
☆20Updated 4 months ago
Alternatives and similar repositories for Digital-Design-Docs
Users that are interested in Digital-Design-Docs are comparing it to the libraries listed below
Sorting:
- LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. (第五届龙芯杯特等奖作…☆37Updated 3 years ago
 - Online judge server for Verilog | verilogoj.ustc.edu.cn☆82Updated last year
 - Uranus MIPS processor by MaxXing & USTB NSCSCC team☆38Updated 5 years ago
 - CQU Dual Issue Machine☆37Updated last year
 - A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Updated 3 years ago
 - nscscc2018☆26Updated 7 years ago
 - Recommended coding standard of Verilog and SystemVerilog.☆35Updated 4 years ago
 - 第一届 RISC-V 中国峰会的幻灯片等资料存放☆38Updated 2 years ago
 - SoC for CQU Dual Issue Machine☆12Updated 3 years ago
 - A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆49Updated last month
 - a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆49Updated last year
 - Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆40Updated 2 years ago
 - High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆82Updated 2 years ago
 - A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated 3 weeks ago
 - Backend & Frontend for JieLabs☆22Updated 2 years ago
 - 龙芯杯21个人赛作品☆35Updated 4 years ago
 - My RV64 CPU (Work in progress)☆19Updated 2 years ago
 - A softcore microprocessor of MIPS32 architecture.☆40Updated last year
 - Run Rocket Chip on VCU128☆30Updated 2 weeks ago
 - 一生一芯的信息发布和内容网站☆135Updated last year
 - ☆35Updated 6 years ago
 - 重庆大学硬件综合设计课程实验文档☆39Updated 3 months ago
 - My knowledge base☆71Updated last week
 - Introduction to Computer Systems (II), Spring 2021☆52Updated 4 years ago
 - The 'missing header' for Chisel☆21Updated 7 months ago
 - A 32-bit 5-stage RISC-V pipeline processor core with traps, S privilege mode, virtual memory, cache, branch prediction and TLB. Powered b…☆15Updated last year
 - BOOM's Simulation Accelerator.☆14Updated 3 years ago
 - 计算机组成原理课程32位监控程序☆50Updated 5 years ago
 - Project template for Artix-7 based Thinpad board☆52Updated last month
 - A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆30Updated 5 years ago