Siudya / NanhuLinks
Open-source high-performance RISC-V processor
☆31Updated 5 months ago
Alternatives and similar repositories for Nanhu
Users that are interested in Nanhu are comparing it to the libraries listed below
Sorting:
- ☆112Updated this week
- 体系结构研讨 + ysyx高阶大纲 (WIP☆187Updated last year
- Comment on the rocket-chip source code☆179Updated 7 years ago
- Modern co-simulation framework for RISC-V CPUs☆159Updated this week
- Modeling Architectural Platform☆212Updated last week
- Wrapper for Rocket-Chip on FPGAs☆138Updated 3 years ago
- Unit tests generator for RVV 1.0☆95Updated last week
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆190Updated last week
- Documentation for RISC-V Spike☆106Updated 7 years ago
- RISC-V Torture Test☆202Updated last year
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆215Updated 5 months ago
- Instruction Set Generator initially contributed by Futurewei☆300Updated 2 years ago
- Run rocket-chip on FPGA☆76Updated this week
- ☆89Updated last month
- RISC-V IOMMU Specification☆141Updated last week
- A matrix extension proposal for AI applications under RISC-V architecture☆155Updated 9 months ago
- A Chisel RTL generator for network-on-chip interconnects☆221Updated last week
- ☆210Updated 7 months ago
- ☆300Updated last week
- This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protectio…☆36Updated last week
- ☆206Updated 4 months ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated this week
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆53Updated 5 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆218Updated 5 years ago
- Documentation for XiangShan Design☆36Updated 3 weeks ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆468Updated 3 months ago
- Vector Acceleration IP core for RISC-V*☆184Updated 6 months ago
- ☆189Updated last year
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆53Updated 3 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆75Updated last month