Alternatives and similar repositories for aura-core

Users that are interested in aura-core are comparing it to the libraries listed below

• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 2 years ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated 3 months ago
• OSCPU / ysyxSoC
  ☆86Updated 2 months ago
• OSCPU / yosys-sta
  ☆73Updated 2 months ago
• ysyx-ta / ysyx-summer-readings
  ☆66Updated 11 months ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• MrAMS / verilogModuleAddPrefix
  verilog module add prefix script 可用于ysyx项目添加学号
  ☆13Updated last year
• ftppz / ShanghaiTech-YSYX
  Unofficial guide for ysyx students applying to ShanghaiTech University
  ☆21Updated 4 months ago
• Heresyrac / Gemmini_doc
  关于移植模型至gemmini的文档
  ☆28Updated 3 years ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆172Updated 9 months ago
• OpenXiangShan / GEM5
  ☆89Updated this week
• Jpz-sdju / trinity
  ☆24Updated 3 months ago
• OSCPU / chisel-playground
  ☆67Updated 5 months ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆51Updated this week
• CherrySprings / CherrySprings
  ☆18Updated 2 years ago
• OpenXiangShan / XiangShan-Design-Doc
  Documentation for XiangShan Design
  ☆29Updated this week
• Clo91eaf / PUA-MIPS
  NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.
  ☆13Updated 3 months ago
• ConvolutedDog / gpgpu-sim-comments
  GPGPU-Sim 中文注释版代码，包含 GPGPU-Sim 模拟器的最新版代码，经过中文注释，以帮助中文用户更好地理解和使用该模拟器。
  ☆19Updated 6 months ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆49Updated 8 months ago
• CmdBlockZQG / rvcore-mini-linux
  Build mini linux for your own RISC-V emulator!
  ☆21Updated 10 months ago
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• lizhirui / DreamCore
  ☆64Updated 2 years ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆68Updated 2 years ago
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆43Updated 2 years ago
• arch-simulator-sig / chisel-env
  Basic chisel difftest environment for RTL design (WIP
  ☆18Updated 4 months ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆147Updated this week
• aaronshappell / tage-predictor
  SystemVerilog implemention of the TAGE branch predictor
  ☆12Updated 4 years ago
• NOP-Processor / NOP-Core
  High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
  ☆81Updated last year
• Rzfly / simple_riscv_soft_core
  This is a simple Risc-v core for software simulation on FPGA.
  ☆8Updated 3 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆65Updated last year