tastynoob / aura-coreLinks
"aura" my super-scalar O3 cpu core
☆25Updated last year
Alternatives and similar repositories for aura-core
Users that are interested in aura-core are comparing it to the libraries listed below
Sorting:
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Updated 3 years ago
- ☆91Updated 3 months ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆32Updated 9 months ago
- ☆67Updated last year
- verilog module add prefix script 可用于ysyx项目添加学号☆13Updated last year
- ☆32Updated 5 months ago
- ☆89Updated 2 months ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last month
- ☆70Updated 11 months ago
- Pick your favorite language to verify your chip.☆75Updated last week
- 体系结构研讨 + ysyx高阶大纲 (WIP☆193Updated last year
- 关于移植模型至gemmini的文档☆32Updated 3 years ago
- ☆122Updated this week
- ☆19Updated 2 years ago
- Unofficial guide for ysyx students applying to ShanghaiTech University☆22Updated 10 months ago
- ☆72Updated 2 years ago
- Modern co-simulation framework for RISC-V CPUs☆166Updated this week
- This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…☆17Updated last year
- Documentation for XiangShan Design☆39Updated this week
- NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.☆13Updated 9 months ago
- Build mini linux for your own RISC-V emulator!☆24Updated last year
- Mirror of https://gitee.com/loongson-edu/open-la500.git☆19Updated last year
- A docker image for One Student One Chip's debug exam☆10Updated 2 years ago
- ☆22Updated 2 years ago
- ☆40Updated 2 years ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆51Updated 3 weeks ago
- A Study of the SiFive Inclusive L2 Cache☆70Updated 2 years ago
- Verilog Implementation of TAGE based predictor by Andre Seznec and Pierre Michaud☆21Updated 7 years ago
- ☆64Updated 3 years ago
- 适用于龙芯杯团队赛入门选手的应急cache模块☆30Updated last year