tastynoob / aura-core
"aura" my super-scalar O3 cpu core
☆24Updated 9 months ago
Alternatives and similar repositories for aura-core:
Users that are interested in aura-core are comparing it to the libraries listed below
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆29Updated 11 months ago
- ☆79Updated 3 weeks ago
- ☆57Updated 2 months ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆49Updated 2 years ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- ☆61Updated 7 months ago
- ☆17Updated last year
- verilog module add prefix script 可用于ysyx项目添加学号☆13Updated last year
- ☆63Updated last month
- Unofficial guide for ysyx students applying to ShanghaiTech University☆21Updated 2 weeks ago
- 关于移植模型至gemmini的文档☆22Updated 2 years ago
- Pick your favorite language to verify your chip.☆39Updated this week
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆47Updated 4 months ago
- ☆22Updated last year
- ☆20Updated last year
- The Scala parser to parse riscv/riscv-opcodes generate☆14Updated last month
- Basic chisel difftest environment for RTL design (WIP☆18Updated this week
- A RISC-V RV32I ISA Single Cycle CPU☆22Updated last year
- ☆74Updated this week
- ☆63Updated 2 years ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆143Updated 4 months ago
- 一生一芯 , ysyx , npc . the repo of the YSYX project . a riscv-64 CPU . writing .☆26Updated 2 years ago
- ☆59Updated last year
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆37Updated last year
- 适用于龙芯杯团队赛入门选手的应急cache模块☆23Updated last year
- This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…☆15Updated 5 months ago
- NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.☆10Updated 11 months ago
- ☆32Updated last year