cassuto / yamp-32

Related projects ⓘ

Alternatives and complementary repositories for yamp-32

• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆25Updated 7 months ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆45Updated 11 months ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated 6 months ago
• fluctlight001 / cpu_for_nscscc2020
  2020龙芯杯个人赛 简易双发射60M（含ibuffer）
  ☆34Updated 4 years ago
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆24Updated 4 months ago
• fluctlight001 / Generic-Cache-Module
  适用于龙芯杯团队赛入门选手的应急cache模块
  ☆22Updated 8 months ago
• NOP-Processor / NOP-Core
  High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
  ☆69Updated last year
• iFuProcessor / iFuCore
  ☆10Updated 3 months ago
• NSCSCC-2020-Fudan / FDU1.1-NSCSCC
  复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品
  ☆40Updated 4 years ago
• Clo91eaf / PUA-MIPS
  NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.
  ☆8Updated 7 months ago
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆34Updated 5 months ago
• HIT-MaRiver-mips / cpucore-mariver
  ☆31Updated last year
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆46Updated 2 years ago
• ysyx-ta / ysyx-summer-readings
  ☆60Updated 3 months ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆43Updated 3 weeks ago
• OSCPU / yosys-sta
  ☆43Updated 4 months ago
• OSCPU / chisel-playground
  ☆56Updated 4 months ago
• huang-jl / LLCL-MIPS
  LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…
  ☆35Updated 2 years ago
• AlwenXXD / nscscc2021
  龙芯杯21个人赛作品
  ☆34Updated 3 years ago
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆121Updated 5 months ago
• Tanggling / BOOMCore
  This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…
  ☆13Updated last month
• OSCPU / ysyxSoC
  ☆76Updated 2 months ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated 8 months ago
• zencove-thu / zencove-zoom
  Highly configurable out-of-order MIPS32 processor, capable of booting Linux.
  ☆37Updated last year
• OpenXiangShan / GEM5
  ☆66Updated this week
• Groupsun / riscv-mini-five-stage
  This is my graduation project, a simple processor soft core, which implements RV32I ISA.
  ☆12Updated 5 years ago
• ftppz / ShanghaiTech-YSYX
  Unofficial guide for ysyx students applying to ShanghaiTech University
  ☆16Updated 4 months ago
• cyyself / CDIM-SoC
  SoC for CQU Dual Issue Machine
  ☆11Updated 2 years ago
• nscscc2019ucas / nscscc2019ucas
  ☆33Updated 5 years ago