ys1998 / spsimLinks
Simulator for a superscalar processor with dynamic scheduling and branch prediction
☆15Updated 7 years ago
Alternatives and similar repositories for spsim
Users that are interested in spsim are comparing it to the libraries listed below
Sorting:
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆15Updated 3 years ago
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆20Updated 8 months ago
- RISC-V Matrix Specification☆23Updated last year
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆30Updated 5 years ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆30Updated this week
- The RTL source for AnyCore RISC-V☆33Updated 3 years ago
- A simulator integrates ChampSim and Ramulator.☆19Updated 4 months ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆31Updated this week
- The official NaplesPU hardware code repository☆20Updated 6 years ago
- DUTH RISC-V Superscalar Microprocessor☆32Updated last year
- RISC-V Superscalar Educational Simulator based on Tomasulo's Algorithm☆27Updated last month
- 5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany☆13Updated 2 weeks ago
- Alpha64 R10000 Two-Way Superscalar Processor☆11Updated 6 years ago
- ☆24Updated 4 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- gem5 FS模式实验手册☆45Updated 2 years ago
- Pipelined 64-bit RISC-V core☆15Updated last year
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆17Updated 4 years ago
- ☆11Updated last year
- ☆22Updated last month
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆53Updated 5 years ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆107Updated 2 months ago
- An out-of-order execution algorithm for pipeline CPU, implemented by verilog☆42Updated 7 years ago
- Example of Chisel3 Diplomacy☆11Updated 3 years ago
- Simple UVM environment for experimenting with Verilator.☆28Updated last month
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆46Updated 6 months ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆19Updated 7 months ago
- Original test vector of RISC-V Vector Extension☆14Updated 4 years ago
- ☆22Updated 2 years ago
- Extremely Simple Microbenchmarks☆37Updated 7 years ago