Alternatives and similar repositories for spsim:

Users that are interested in spsim are comparing it to the libraries listed below

• GabbedT / ApogeoRV
  A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.
  ☆16Updated 2 weeks ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆29Updated 2 months ago
• wshenyi / EECS-470-FinalProject
  A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.
  ☆10Updated 2 years ago
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆30Updated 2 years ago
• joey1115 / Alpha64_R10000_Superscalar_Processor
  Alpha64 R10000 Two-Way Superscalar Processor
  ☆11Updated 5 years ago
• esa-tu-darmstadt / SCAIE-V
  An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:
  ☆14Updated 10 months ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆29Updated 8 months ago
• YanB25 / Tomasulo
  An out-of-order execution algorithm for pipeline CPU, implemented by verilog
  ☆36Updated 6 years ago
• oscc-ip / sdram
  An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …
  ☆14Updated this week
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆49Updated 3 years ago
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆25Updated this week
• RISMicroDevices / CHIron
  Open-source AMBA CHI infrastructures (supporting Issue B, E.b)
  ☆13Updated this week
• RPTU-EIS / RISCV-Core
  5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany
  ☆11Updated 6 months ago
• antmicro / astsee
  ☆12Updated 6 months ago
• MikeCovrado / GettingVerilatorStartedWithUVM
  Simple UVM environment for experimenting with Verilator.
  ☆13Updated 2 weeks ago
• jieltan / OpenCompArchCourse
  ☆20Updated 3 years ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆25Updated 3 months ago
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆18Updated 3 months ago
• chipsalliance / tilelink
  ☆27Updated last month
• GeekAlexis / superscalar-mips
  A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines
  ☆11Updated 5 years ago
• THU-DSP-LAB / ventus-gpgpu-cpp-simulator
  Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus
  ☆20Updated 5 months ago
• nju-mips / noop-lo
  A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
  ☆26Updated 4 years ago
• rivosinc / hammer
  Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
  ☆25Updated last year
• Xilinx / pcie-model
  PCI Express controller model
  ☆47Updated 2 years ago
• pulp-platform / axi_llc
  ☆21Updated last week
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated 10 months ago
• miaochenlu / Gem5_tutorials
  ☆18Updated last year
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆30Updated last year
• CMU-SAFARI / Virtuoso
  Virtuoso is a new simulator that focuses on modelling various memory management and virtual memory aspects.
  ☆28Updated last year