ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis
☆33Feb 20, 2024Updated 2 years ago
Alternatives and similar repositories for arch-explorer
Users that are interested in arch-explorer are comparing it to the libraries listed below
Sorting:
- ☆17Apr 16, 2024Updated last year
- The open-sourced version of BOOM-Explorer☆45May 31, 2023Updated 2 years ago
- ☆64Dec 4, 2022Updated 3 years ago
- Fuzzing General-Purpose Hardware Designs with Software Fuzzers☆24Jan 11, 2026Updated last month
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆31May 12, 2023Updated 2 years ago
- ☆13May 8, 2025Updated 9 months ago
- ☆26Oct 6, 2023Updated 2 years ago
- ☆22Nov 3, 2025Updated 3 months ago
- Contains the code for the Flexus cycle-accurate simulator, used in QFlex.☆14Updated this week
- Criticality-aware Framework for Modeling Computer Performance☆33Dec 15, 2024Updated last year
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆16Sep 27, 2022Updated 3 years ago
- This is a repo to store circuit design datasets☆19Jan 17, 2024Updated 2 years ago
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆20Apr 7, 2025Updated 10 months ago
- 给NEMU移植Linux Kernel!☆22Jun 1, 2025Updated 9 months ago
- A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arx…☆23Jun 30, 2024Updated last year
- Basic chisel difftest environment for RTL design (WIP☆20Mar 8, 2025Updated 11 months ago
- HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs☆39Dec 9, 2024Updated last year
- Luthier, a GPU binary instrumentation tool for AMD GPUs☆27Feb 21, 2026Updated last week
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Nov 24, 2025Updated 3 months ago
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆25Nov 26, 2025Updated 3 months ago
- ordspecsim: The Swarm architecture simulator☆24Feb 15, 2023Updated 3 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆11May 6, 2019Updated 6 years ago
- Simulator for a superscalar processor with dynamic scheduling and branch prediction☆15Nov 23, 2018Updated 7 years ago
- Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…☆22Mar 29, 2025Updated 11 months ago
- An example of an eBPF program hooking into the kill tracepoint☆22May 26, 2023Updated 2 years ago
- Simulator code of the paper "Dissecting and Modeling the Architecture of Modern GPU Cores"☆64Oct 15, 2025Updated 4 months ago
- ☆66Aug 5, 2024Updated last year
- Unofficial guide for ysyx students applying to ShanghaiTech University☆23Feb 25, 2025Updated last year
- Recommended coding standard of Verilog and SystemVerilog.☆36Oct 21, 2021Updated 4 years ago
- ☆11Nov 14, 2023Updated 2 years ago
- ☆14Dec 27, 2024Updated last year
- Control Logic Synthesis: Drawing the Rest of the OWL☆13Jun 17, 2024Updated last year
- My second attempt at a RISC-V CPU with learnings form my previous attempt.☆10Apr 29, 2024Updated last year
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆21Apr 25, 2025Updated 10 months ago
- A docker image for One Student One Chip's debug exam☆10Sep 22, 2023Updated 2 years ago
- ☆14Oct 30, 2024Updated last year
- A cache simulator designed to be used with memory access traces obtained from Pin (www.pintool.org)☆23Aug 21, 2018Updated 7 years ago
- ☆78Oct 29, 2024Updated last year
- Introduction to homotopy type theory (reading course), LP2 2023, offered via DAT235/DIT577: Research-oriented course in Computer Science …☆14Apr 17, 2024Updated last year