Alternatives and similar repositories for 3d-placer:

Users that are interested in 3d-placer are comparing it to the libraries listed below

• coherent17 / 2022-ICCAD-Problem-B
  Problem B: 3D Placement with D2D Vertical Connections
  ☆9Updated 2 years ago
• bu-icsg / TAP-2.5D
  ☆27Updated 3 years ago
• EricLu1218 / Physical_Design_Automation
  2019 NTHU CS6135 (CS613500) VLSI Physical Design Automation Course Projects (include Two-way Min-cut Partitioning, Fixed-outline Slicing …
  ☆34Updated this week
• jacky860226 / ICCAD-2021-B
  ICCAD-2021-B
  ☆12Updated 3 years ago
• ycchen218 / EDA-IRdrop-Prediction
  This is a deep-learning based model for Electronic Design Automation(EDA), predicting the IR drop location on the chip.
  ☆27Updated last year
• recurme / Mixed-Cell-Height_legalizer
  ☆10Updated 8 months ago
• VidyaChhabria / ThermEDGe-and-IREDGe
  Encoder-decoder based generative networks for static and transient thermal analysis
  ☆19Updated 2 years ago
• jkim971201 / SkyPlace
  ☆16Updated 6 months ago
• Daikon-Sun / Physical-Design-for-Nanometer-ICs
  Assignments of Physical Design for Nanometer ICs (Spring 2017, Prof. Yao-Wen Chang)
  ☆39Updated 6 years ago
• asyncvlsi / lefdef
  Mirror of the Si2 LEF/DEF parser (v5.8)
  ☆13Updated 3 years ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆52Updated 4 months ago
• liangrj2014 / ISPD24_contest
  ☆20Updated 2 months ago
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆101Updated last year
• geziangfinn / easyPlace
  Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS
  ☆31Updated 4 months ago
• tsung-wei-huang / ece5960-physical-design
  ☆38Updated 2 years ago
• UMN-EDA / BeGAN-benchmarks
  ☆24Updated last year
• UTDA-group / BoxRouter
  BoxRouter2.0 is a new global router for ultimate routability. It is inspired by BoxRouter [1], but can perform multi-layer routing with 2…
  ☆20Updated 6 years ago
• sathvikbhat / vlsi_physical_design_automation
  A project to perform the VLSI Physical Design Flow steps of partitioning, floorplan, placement and routing.
  ☆11Updated 3 years ago
• ABKGroup / BlobPlacement
  ☆11Updated 9 months ago
• ABKGroup / TritonPart
  The first version of TritonPart
  ☆24Updated last year
• magical-eda / UT-AnLay
  Analog Placement Quality Prediction
  ☆20Updated 2 years ago
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆37Updated last year
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆44Updated 6 months ago
• baichen318 / FreePDK45
  This is the FreePDK45 V1.4 Process Development Kit for the 45 nm technology
  ☆23Updated 4 years ago
• NTU-LaDS-II / FAN_ATPG
  FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
  ☆86Updated last year
• lamda-bbo / Efficient-TDP
  Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".
  ☆29Updated last month
• cuhk-eda / cu-gr-2
  ☆44Updated last year
• abk-openroad / BST-DME
  Bounded-Skew DME v1.3
  ☆14Updated 6 years ago
• cuhk-eda / ripple
  Pin-Accessible Legalization for Mixed-Cell-Height Circuits
  ☆26Updated 3 years ago
• PKU-IDEA / SAGERoute
  SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility (DATE2023)
  ☆20Updated last year