Moorvan / ChiselFV

Related projects: ⓘ

• ekiwi / open-source-formal-verification-for-chisel
  ☆12Updated 2 years ago
• gpt4rtl / AutoSVA2
  ☆12Updated 10 months ago
• amahzoon / genmul
  ☆14Updated 3 years ago
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆12Updated 2 months ago
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆16Updated 3 months ago
• iscas-tis / CHA
  ☆14Updated 2 months ago
• rajdeep87 / verilog-c
  ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.
  ☆13Updated 5 years ago
• PrincetonUniversity / IMDb-Archive
  ILA Model Database
  ☆20Updated 3 years ago
• fangwenji / tacas23-wasim
  ☆12Updated last year
• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆17Updated 11 months ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆61Updated 3 years ago
• chengyinwu / QuteRTL
  QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification
  ☆13Updated 7 years ago
• ehw-fit / ariths-gen
  Generator of arithmetic circuits (multipliers, adders) and approximate circuits
  ☆26Updated last month
• wjrforcyber / ABCPaperCheck
  Research paper based on or related to ABC.
  ☆14Updated this week
• amamory-verification / hw-formal-verif
  Hardware Formal Verification
  ☆14Updated 4 years ago
• morenes / AutoCC
  Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…
  ☆11Updated last year
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆28Updated 3 months ago
• sterin / super-prove-build
  ☆11Updated 4 years ago
• hammad-a / verilog_repair
  Automated Repair of Verilog Hardware Descriptions
  ☆25Updated 5 months ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆72Updated 5 months ago
• Yu-Maryland / Verilog-to-PyG
  ☆18Updated 4 months ago
• scale-lab / BACS
  Benchmarks for Approximate Circuit Synthesis
  ☆12Updated 4 years ago
• SJTU-ECTL / ALSRAC
  ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set
  ☆17Updated 11 months ago
• hkust-zhiyao / RTL-Timer
  Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
  ☆15Updated 2 months ago
• tdb-alcorn / chisel-formal
  ☆23Updated 3 years ago
• arminbiere / aiger
  AIGER And-Inverter-Graph Library
  ☆57Updated 3 months ago
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆22Updated 4 years ago
• efeslab / hardware-bugbase
  ☆16Updated 3 months ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆82Updated 9 months ago
• HKUST-GZ-VLSI / Design-Dataset
  This is a repo to store circuit design datasets
  ☆15Updated 8 months ago