Alternatives and similar repositories for simplecar

Users that are interested in simplecar are comparing it to the libraries listed below

• CoriolisSP / FuzzBtor2
  Random Generator of Btor2 Files
  ☆10Updated 2 years ago
• mgudemann / iimc
  ☆14Updated 7 years ago
• hwmcc / btor2tools
  A generic parser and tool package for the BTOR2 format.
  ☆43Updated last month
• iscas-tis / CHA
  ☆19Updated last year
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆26Updated last year
• jetafese / btor2mlir
  Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification
  ☆20Updated last month
• yaohsiaopid / rtl2uspec
  ☆11Updated 4 months ago
• gipsyh / rIC3-HWMCC24
  rIC3 model checker for Hardware Model Checking Competition 2024(HWMCC'24) submission
  ☆12Updated 3 months ago
• Moorvan / RISCV-Formal-Chisel
  RISC-V Formal in Chisel
  ☆12Updated last year
• d-kfmnn / amulet2
  AMulet 2. - A better AIG Multiplier Examination Tool
  ☆26Updated 3 years ago
• ycunxi / ACEC_benchmarks
  Arithmetic multiplier benchmarks
  ☆11Updated 7 years ago
• aman-goel / avr
  Reads a state transition system and performs property checking
  ☆88Updated last month
• ekiwi / open-source-formal-verification-for-chisel
  ☆10Updated 4 years ago
• pddenhar / Z3-IC3-PDR
  Implementation of the IC3 / Property Directed Reachability algorithm using the the Z3 SMT solver.
  ☆16Updated 9 years ago
• rajdeep87 / verilog-c
  ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.
  ☆17Updated 6 years ago
• temelmertcan / multgen
  Integer Multiplier Generator for Verilog
  ☆23Updated 3 months ago
• arbrad / IC3ref
  IC3 reference implementation: a short, simple, fairly competitive implementation of IC3. Read it, tune it, extend it, play with it.
  ☆61Updated 10 years ago
• stanford-centaur / pono
  Pono: A flexible and extensible SMT-based model checker
  ☆112Updated 2 weeks ago
• jix / kissat_extras
  A fork of the Kissat SAT solver with additional features. Supports incremental solving.
  ☆17Updated 3 years ago
• upscale-project / generic-sqed-demo
  ☆13Updated 4 years ago
• RafaelTupynamba / SMTSampler
  SMTSampler: Efficient Stimulus Generation from Complex SMT Constraints
  ☆29Updated 6 years ago
• JKomp / AIGER
  Python version of tools to work with AIG formatted files
  ☆12Updated 5 months ago
• gipsyh / rIC3
  Hardware Formal Verification Tool
  ☆71Updated this week
• chc-comp / chc-tools
  Tools for manipulating CHC and related files
  ☆15Updated 2 years ago
• jar-ben / mustool
  ☆15Updated 2 years ago
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆90Updated this week
• fangwenji / tacas23-wasim
  ☆12Updated 2 years ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆74Updated 5 years ago
• saleh1204 / sis
  Logic Synthesis System from UC Berkeley (Unofficial Distribution)
  ☆15Updated 6 years ago
• mit-plv / hemiola
  A Coq framework to support structural design and proof of hardware cache-coherence protocols
  ☆14Updated 3 years ago