Alternatives and similar repositories for SMT-based-STDCELL-Layout-Generator:

Users that are interested in SMT-based-STDCELL-Layout-Generator are comparing it to the libraries listed below

• ckchengucsd / SMT-based-STDCELL-Layout-Generator-for-PROBE2.0
  SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0
  ☆17Updated 4 years ago
• jinwookjungs / open_design_flow
  OpenDesign Flow Database
  ☆16Updated 6 years ago
• magical-eda / MAGICAL-CIRCUITS
  Circuit release of the MAGICAL project
  ☆35Updated 5 years ago
• USCPOSH / AMPSE
  This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…
  ☆24Updated 2 years ago
• ABKGroup / PROBE3.0
  ☆43Updated last year
• ALIGN-analoglayout / AnalogDetailedRouter
  Intel's Analog Detailed Router
  ☆38Updated 5 years ago
• ieee-ceda-datc / datc-rdf-Metrics4ML
  ☆30Updated 3 years ago
• jinwookjungs / lefdef_util
  A LEF/DEF Utility.
  ☆28Updated 5 years ago
• ABKGroup / RosettaStone
  ☆25Updated 2 years ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆37Updated 5 years ago
• Ravenslofty / librecell
  ☆23Updated 3 years ago
• TILOS-AI-Institute / MLCAD-2023-FPGA-Macro-Placement-Contest
  ☆29Updated last year
• ChrisZonghaoLi / sky130_ldo_rl
  This repo contains the code that runs RL+GNN to optimize LDOs in SKY130 process.
  ☆35Updated 9 months ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆49Updated 4 years ago
• lrakai / gate-sizing
  Optimal gate sizing of digital circuits using geometric programming
  ☆9Updated 8 years ago
• zslwyuan / AutoCellLibX
  AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining
  ☆13Updated 2 years ago
• AUCOHL / OGRE
  Global Router Built for ICCAD Contest 2019
  ☆30Updated 5 years ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆54Updated 5 months ago
• ABKGroup / PROBE_SMT_AutoCell
  ☆18Updated last year
• electronics-and-drives / MLCAD22
  Source code for the Paper: "Deep Reinforcement Learning for Analog Circuit Sizing with an Electrical Design Space and Sparse Rewards"
  ☆12Updated 2 years ago
• abk-openroad / BST-DME
  Bounded-Skew DME v1.3
  ☆14Updated 6 years ago
• eclufsc / libertyParser
  Mirror of Synopsys's Liberty parser library
  ☆20Updated 6 years ago
• aolofsson / IDEA
  ☆34Updated 5 years ago
• IntelLabs / FloorSet
  ☆71Updated 4 months ago
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆54Updated 4 years ago
• magical-eda / UT-AnLay
  Analog Placement Quality Prediction
  ☆21Updated 2 years ago
• parkerluxu / awesome-Analog-IC-Design-Automation
  awesome-Analog-IC-Design-Automation
  ☆34Updated last year
• CODA-Team / AnalogGym
  ☆37Updated last month
• marlls1989 / ascend-freepdk45
  A free standard cell library for SDDS-NCL circuits
  ☆27Updated 2 years ago
• The-OpenROAD-Project-Attic / OpenROAD-Utilities
  Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project
  ☆19Updated 5 years ago