intel / rohd-cosim
Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators
☆23Updated last month
Alternatives and similar repositories for rohd-cosim:
Users that are interested in rohd-cosim are comparing it to the libraries listed below
- The ROHD Verification Framework is a hardware verification framework built upon ROHD for building testbenches.☆41Updated 3 months ago
- A hardware component library developed with ROHD.☆93Updated last week
- SystemVerilog modules and classes commonly used for verification☆46Updated 2 months ago
- A SystemVerilog source file pickler.☆56Updated 5 months ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆67Updated this week
- WAL enables programmable waveform analysis.☆147Updated last month
- ☆31Updated 2 months ago
- Python Tool for UVM Testbench Generation☆52Updated 10 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆63Updated 3 months ago
- General Purpose AXI Direct Memory Access☆48Updated 10 months ago
- Python bindings for slang, a library for compiling SystemVerilog☆55Updated 2 months ago
- SystemVerilog frontend for Yosys☆81Updated 2 weeks ago
- ☆25Updated 2 weeks ago
- This repository is compilation of basics of System Verilog Assertions in context of formal verification☆20Updated 6 years ago
- ☆89Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 10 months ago
- SystemVerilog Linter based on pyslang☆29Updated 2 months ago
- Open source process design kit for 28nm open process☆51Updated 11 months ago
- Generic Register Interface (contains various adapters)☆111Updated 6 months ago
- SystemVerilog RTL Linter for YoSys☆20Updated 4 months ago
- Python interface for cross-calling with HDL☆31Updated 2 weeks ago
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆44Updated 4 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆65Updated 4 years ago
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆38Updated last week
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated 10 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated 7 months ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆25Updated 4 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆26Updated 6 months ago
- An open source, parameterized SystemVerilog digital hardware IP library☆26Updated 10 months ago
- Structural Netlist API (and more) for EDA post synthesis flow development☆93Updated this week