Alternatives and similar repositories for rohd-cosim:

Users that are interested in rohd-cosim are comparing it to the libraries listed below

• intel / rohd-vf
  The ROHD Verification Framework is a hardware verification framework built upon ROHD for building testbenches.
  ☆33Updated 3 weeks ago
• intel / rohd-hcl
  A hardware component library developed with ROHD.
  ☆84Updated last week
• openformal / sva_basics
  This repository is compilation of basics of System Verilog Assertions in context of formal verification
  ☆20Updated 5 years ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆80Updated 8 months ago
• vinayrayapati / iiitb_rv32i
  ☆13Updated 2 years ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆38Updated 4 years ago
• nickson-jose / vsdstdcelldesign
  This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…
  ☆64Updated 4 years ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆33Updated 2 months ago
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆79Updated 2 months ago
• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆43Updated 4 years ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆50Updated 8 months ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆48Updated 3 weeks ago
• spider-tronix / Standard-Cell-Characterization
  Open Source tool to build liberty files and for Characterizing Standard Cells.
  ☆24Updated 3 years ago
• manili / VSDBabySoC
  VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
  ☆36Updated 3 years ago
• vsdip / vsdsram_sky130
  ☆40Updated 2 years ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆56Updated 3 years ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆46Updated this week
• hanysalah / Design-Pattern-in-SV
  This repo is created to include illustrative examples on object oriented design pattern in SV
  ☆55Updated last year
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆45Updated 3 weeks ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆64Updated 3 years ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆54Updated 3 months ago
• chipsalliance / uvm-verilator
  ☆82Updated last year
• shariethernet / Physical-Design-with-OpenLANE-using-SKY130-PDK
  This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…
  ☆41Updated 3 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆48Updated 8 months ago
• snbk001 / 100DaysofRTL
  100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…
  ☆32Updated 2 years ago
• praharshapm / vsdmixedsignalflow
  This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…
  ☆42Updated 4 years ago
• antmicro / verilator-verification-features-tests
  ☆17Updated this week
• amiq-consulting / amiq_eth
  Library defining all Ethernet packets in SystemVerilog and in SystemC
  ☆36Updated 8 years ago
• AsFigo / yoYoLint
  SystemVerilog RTL Linter for YoSys
  ☆18Updated 2 months ago
• akilm / Physical-Design
  Physical Design Flow from RTL to GDS using Opensource tools.
  ☆88Updated 4 years ago