johnjohnlin / nicotbLinks
A lightweight library to perform Python/Verilog co-simulation with Python3.3 coroutine + numpy. The name Nicotb cames from NatIve COroutine TestBench.
☆21Updated last year
Alternatives and similar repositories for nicotb
Users that are interested in nicotb are comparing it to the libraries listed below
Sorting:
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- Python wrapper for verilator model☆84Updated last year
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆36Updated 2 weeks ago
- Educational Design Kit for Synopsys Tools with a set of Characterized Standard Cell Library☆33Updated 3 years ago
- Python library for parsing module definitions and instantiations from SystemVerilog files☆23Updated 4 years ago
- use pivpi to drive testbench event☆21Updated 8 years ago
- Running Python code in SystemVerilog☆69Updated this week
- SystemVerilog & Verilog Module I/O parser and printer☆25Updated 3 years ago
- This is a tutorial on standard digital design flow☆78Updated 4 years ago
- YosysHQ SVA AXI Properties☆39Updated 2 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆83Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 3 months ago
- SystemVerilog Functional Coverage for RISC-V ISA☆28Updated this week
- ideas and eda software for vlsi design☆50Updated last week
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆23Updated 6 years ago
- Open Source PHY v2☆28Updated last year
- VeRLPy is an open-source python library developed to improve the digital hardware verification process by using Reinforcement Learning (R…☆26Updated 2 years ago
- ☆44Updated 5 years ago
- Python bindings for slang, a library for compiling SystemVerilog☆58Updated 4 months ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆31Updated last year
- SystemVerilog package for reading, manipulating, and writing JSON-formatted data☆10Updated 3 years ago
- This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…☆28Updated last year
- Code snippets from articles published on www.amiq.com/consulting/blog☆36Updated 11 months ago
- ☆19Updated 10 years ago
- SystemVerilog modules and classes commonly used for verification☆48Updated 5 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆41Updated 2 years ago
- An open source generator for standard cell based memories.☆13Updated 8 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- Python Tool for UVM Testbench Generation☆53Updated last year