A lightweight library to perform Python/Verilog co-simulation with Python3.3 coroutine + numpy. The name Nicotb cames from NatIve COroutine TestBench.
☆21Dec 24, 2023Updated 2 years ago
Alternatives and similar repositories for nicotb
Users that are interested in nicotb are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆15Jan 9, 2017Updated 9 years ago
- Eric's branch of Doxverilog (doxygen + doxverilog patch)☆15Jun 6, 2012Updated 14 years ago
- Verification Template Engine is a Jinja2-based template engine targeted at verification engineers☆14Jan 4, 2024Updated 2 years ago
- Running Python code in SystemVerilog☆73May 8, 2026Updated 2 months ago
- Python wrapper for verilator model☆94Feb 10, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Debuggable hardware generator☆71Feb 17, 2023Updated 3 years ago
- Handle Fast Signal Traces (fst) in Python☆16Jun 11, 2025Updated last year
- SystemVerilog & Verilog Module I/O parser and printer☆26Jul 1, 2026Updated 3 weeks ago
- GDB server to debug CPU simulation waveform traces☆43Feb 21, 2022Updated 4 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆25Jul 14, 2020Updated 6 years ago
- Digital Standard Cells based SAR ADC☆15Aug 5, 2021Updated 4 years ago
- ☆20Mar 6, 2022Updated 4 years ago
- The ZipCPU blog☆19Updated this week
- micro version of cocotb, to run on microcontrollers or desktop to get hardware in the loop☆25Feb 25, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Synthesiser for Asynchronous Verilog Language☆20Oct 29, 2014Updated 11 years ago
- Source code for the Paper: "Deep Reinforcement Learning for Analog Circuit Sizing with an Electrical Design Space and Sparse Rewards"☆15Sep 12, 2022Updated 3 years ago
- A verilog parser☆19Apr 12, 2024Updated 2 years ago
- A flexible framework for analyzing and transforming FPGA netlists. Official repository.☆113Apr 27, 2026Updated 2 months ago
- ☆24Feb 15, 2013Updated 13 years ago
- UVM verification kits which uses YASA as simulation script☆19Dec 10, 2019Updated 6 years ago
- BlockCIrculantRNN (LSTM and GRU) using TensorFlow☆14Oct 30, 2018Updated 7 years ago
- Verilog parsing and generator crate.☆22Apr 16, 2020Updated 6 years ago
- DMA source and sink blocks for Xilinx Zynq FPGAs☆24May 19, 2020Updated 6 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Artifacts for the SCVP lecture☆12Nov 17, 2021Updated 4 years ago
- Huffman encoder☆10Sep 8, 2013Updated 12 years ago
- Cycle accurate MC6502 compatible processor in Verilog.☆16Oct 11, 2021Updated 4 years ago
- Test dashboard for verification features in Verilator☆33Updated this week
- Code needed to reproduce results from my ICLR 2019 paper on fixed-point quantization of the backprop algorithm.☆10Jan 24, 2019Updated 7 years ago
- SMT-based-STDCELL-Layout-Generator☆20Sep 30, 2021Updated 4 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆33May 26, 2024Updated 2 years ago
- GNN-RE datasets for circuit recognition☆59May 16, 2023Updated 3 years ago
- Tutorials on HLS Design☆51Jan 16, 2020Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Embedded UVM (D Language port of IEEE UVM 1.0)☆34Nov 6, 2025Updated 8 months ago
- [deprecated]use mshr-h/vscode-verilog-hdl-support☆24Nov 3, 2018Updated 7 years ago
- ☆17Feb 9, 2023Updated 3 years ago
- Modified UEFI ROMs for macOS support☆11Sep 19, 2024Updated last year
- Long Short-Term Memory Neural Networks trained and tested on the TIMIT Acoustic-Phonetic Continuous Speech Corpus.☆11Aug 27, 2017Updated 8 years ago
- Designed for flash/non flash models. Supports LCD with backlight, LiPo charge, USB slave, USB in.☆11Sep 7, 2017Updated 8 years ago
- p5js library for projection mapping☆16Dec 2, 2021Updated 4 years ago