johnjohnlin / nicotb
A lightweight library to perform Python/Verilog co-simulation with Python3.3 coroutine + numpy. The name Nicotb cames from NatIve COroutine TestBench.
☆21Updated last year
Alternatives and similar repositories for nicotb:
Users that are interested in nicotb are comparing it to the libraries listed below
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆31Updated this week
- use pivpi to drive testbench event☆20Updated 8 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆35Updated 2 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆33Updated 3 months ago
- SystemVerilog Functional Coverage for RISC-V ISA☆25Updated 4 months ago
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆43Updated 4 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- SystemVerilog & Verilog Module I/O parser and printer☆25Updated 3 years ago
- ☆24Updated 5 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆26Updated 8 months ago
- Project repo for the POSH on-chip network generator☆43Updated last year
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- sram/rram/mram.. compiler☆30Updated last year
- Running Python code in SystemVerilog☆67Updated 7 months ago
- This is a tutorial on standard digital design flow☆73Updated 3 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆37Updated 5 months ago
- YosysHQ SVA AXI Properties☆37Updated 2 years ago
- AMC: Asynchronous Memory Compiler☆48Updated 4 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆76Updated 10 months ago
- An open source generator for standard cell based memories.☆13Updated 8 years ago
- Educational Design Kit for Synopsys Tools with a set of Characterized Standard Cell Library☆31Updated 3 years ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆21Updated 6 years ago
- Open Source PHY v2☆25Updated 9 months ago
- Implementation of post-process coverage, and batch waveform search☆15Updated 3 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 7 months ago
- Python library for parsing module definitions and instantiations from SystemVerilog files☆22Updated 3 years ago
- Useful UVM extensions☆21Updated 7 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- hardware library for hwt (= ipcore repo)☆37Updated 3 months ago