johnjohnlin / nicotbLinks
A lightweight library to perform Python/Verilog co-simulation with Python3.3 coroutine + numpy. The name Nicotb cames from NatIve COroutine TestBench.
☆21Updated last year
Alternatives and similar repositories for nicotb
Users that are interested in nicotb are comparing it to the libraries listed below
Sorting:
- This is a tutorial on standard digital design flow☆78Updated 4 years ago
- Python wrapper for verilator model☆88Updated last year
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆88Updated last year
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆46Updated 4 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆28Updated last year
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆27Updated 4 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- ideas and eda software for vlsi design☆50Updated last week
- Running Python code in SystemVerilog☆70Updated 2 months ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated 2 months ago
- YosysHQ SVA AXI Properties☆42Updated 2 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆113Updated last year
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆127Updated 2 years ago
- ☆41Updated 7 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆38Updated 2 months ago
- Modular Multi-ported SRAM-based Memory☆31Updated 9 months ago
- ☆44Updated 5 years ago
- [WIP] Dockerize Synopsys/Cadence EDA tools☆90Updated 6 years ago
- SystemVerilog modules and classes commonly used for verification☆50Updated 7 months ago
- Python packages providing a library for Verification Stimulus and Coverage☆126Updated last month
- ☆97Updated last year
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- Project repo for the POSH on-chip network generator☆50Updated 5 months ago
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 9 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆18Updated last year
- Implementation of post-process coverage, and batch waveform search☆15Updated 4 years ago
- VeRLPy is an open-source python library developed to improve the digital hardware verification process by using Reinforcement Learning (R…☆27Updated 2 years ago
- use pivpi to drive testbench event☆21Updated 9 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated 3 months ago