A Verilog Filelist parser in Rust
☆11Mar 25, 2022Updated 3 years ago
Alternatives and similar repositories for verilog-filelist-parser
Users that are interested in verilog-filelist-parser are comparing it to the libraries listed below
Sorting:
- SystemVerilog package for reading, manipulating, and writing JSON-formatted data☆12Feb 19, 2022Updated 4 years ago
- SystemVerilog Extension Library -- a library of utilities for generic programming and increased productivity☆34Jul 27, 2024Updated last year
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆23Jul 12, 2023Updated 2 years ago
- Bazel build rules for compiling Verilog☆22Mar 4, 2024Updated 2 years ago
- Cross platform Instant Outbidding Bot, Instant Outbidder Bot is designed to outbid all real-time bids within a second by percentage incre…☆100Jan 17, 2023Updated 3 years ago
- Verilog parsing and generator crate.☆21Apr 16, 2020Updated 5 years ago
- A proof-of-concept, Rust-inspired, declarative hardware description language optimized for RTL coding☆22Mar 3, 2025Updated last year
- A concolic testing engine for RISC-V embedded software with support for SystemC peripherals☆27Oct 4, 2023Updated 2 years ago
- SystemVerilog & Verilog Module I/O parser and printer☆25Jul 25, 2021Updated 4 years ago
- Artifacts for the SCVP lecture☆12Nov 17, 2021Updated 4 years ago
- Debuggable hardware generator☆71Feb 17, 2023Updated 3 years ago
- Python bindings for slang, a library for compiling SystemVerilog☆66Jan 18, 2025Updated last year
- Verilog generation tool written in Rust☆62Jun 29, 2023Updated 2 years ago
- Functional Verification of Physical Layer of PCI Express Gen5.0 Graduation Project Using UVM☆25Jul 17, 2025Updated 7 months ago
- Log file scanner used with EDA tools to classify errors and warnings☆12Nov 14, 2022Updated 3 years ago
- A LEF/DEF Utility.☆34Aug 15, 2019Updated 6 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Dec 24, 2024Updated last year
- ☆11Apr 25, 2020Updated 5 years ago
- PSSGen: Portable Test and Stimulus Standard DSL Generator☆14Dec 29, 2025Updated 2 months ago
- UVM components for DSP tasks (MODulation/DEModulation)☆14Mar 2, 2022Updated 4 years ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆463Nov 4, 2025Updated 4 months ago
- Sequence Planner☆12Nov 17, 2017Updated 8 years ago
- A Terraria clone in Python, just for fun☆10Jun 7, 2020Updated 5 years ago
- Translate a subset of C to Verilog☆12May 8, 2019Updated 6 years ago
- A linearizability checker for concurrent data structures☆12Aug 3, 2023Updated 2 years ago
- benchmarking e-graph extraction☆50Feb 2, 2026Updated last month
- Convert Xilinx FPGA bitstream from the .bit format (as generated by Vivado) into the .bin format (as expected by Linux fpga_manager)☆14Sep 5, 2023Updated 2 years ago
- A copy of the latest version of MVSIS☆12Apr 18, 2021Updated 4 years ago
- Experimental Nix implementation of Android `soong` modules☆10Oct 11, 2023Updated 2 years ago
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- xDEVS: A cross-platform Discrete EVent System simulator☆14Nov 14, 2025Updated 3 months ago
- Controlled Invariant Sets in Two Moves☆14Dec 21, 2021Updated 4 years ago
- Source code for LEF/DEF☆11Oct 16, 2018Updated 7 years ago
- Implementation of the UsbBus trait of usb-device, which simulates a Bus as a USBIP Server. Useful for developing UsbClass traits and simu…☆18Nov 15, 2023Updated 2 years ago
- A fork of Yosys that integrates the CellIFT pass☆13Jul 23, 2025Updated 7 months ago
- Track the origin of your json values for better error reporting!☆16Oct 10, 2020Updated 5 years ago
- my nix-darwin config☆13Feb 24, 2026Updated last week
- BuDDy BDD package (with CMake support)☆15May 7, 2024Updated last year
- An demonic library to write PE binaries☆11Feb 12, 2024Updated 2 years ago