Alternatives and similar repositories for verilog-filelist-parser

Users that are interested in verilog-filelist-parser are comparing it to the libraries listed below

• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆42Updated 2 years ago
• ucb-substrate / substrate2
  21st century electronic design automation tools, written in Rust.
  ☆31Updated last week
• amamory-verification / hw-formal-verif
  Hardware Formal Verification
  ☆15Updated 5 years ago
• Kuree / hgdb
  Hardware generator debugger
  ☆75Updated last year
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆47Updated 11 months ago
• cclienti / svmodule
  SystemVerilog & Verilog Module I/O parser and printer
  ☆25Updated 4 years ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆59Updated 10 months ago
• Kuree / kratos
  Debuggable hardware generator
  ☆69Updated 2 years ago
• openformal / sva_basics
  This repository is compilation of basics of System Verilog Assertions in context of formal verification
  ☆24Updated 6 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆65Updated 9 months ago
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated 4 months ago
• leonardt / fault
  A Python package for testing hardware (part of the magma ecosystem)
  ☆43Updated last year
• Nic30 / hwtHls
  LLVM based HLS library for HWToolkit (hardware devel. toolkit)
  ☆25Updated last month
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆62Updated 7 months ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆27Updated 5 years ago
• fukatani / Pyverilog_toolbox
  ☆41Updated 7 years ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆45Updated 3 weeks ago
• vegaluisjose / vast
  Verilog AST
  ☆21Updated last year
• MikeCovrado / GettingVerilatorStartedWithUVM
  Simple UVM environment for experimenting with Verilator.
  ☆23Updated 4 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆30Updated 3 months ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆62Updated 4 years ago
• chipsalliance / fpga-interchange-schema
  ☆56Updated 3 years ago
• Kuree / cgra_pnr
  Fast PnR toolchain for CGRA
  ☆18Updated last year
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆50Updated 4 months ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated 3 weeks ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆54Updated 2 weeks ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆70Updated 2 months ago
• chipsalliance / uvm-verilator
  ☆97Updated last year
• Lampro-Mellon / Quasar
  Quasar 2.0: Chisel equivalent of SweRV-EL2
  ☆30Updated 4 years ago