A Verilog Filelist parser in Rust
☆11Mar 25, 2022Updated 4 years ago
Alternatives and similar repositories for verilog-filelist-parser
Users that are interested in verilog-filelist-parser are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆23Jul 12, 2023Updated 2 years ago
- SystemVerilog Extension Library -- a library of utilities for generic programming and increased productivity☆34Mar 28, 2026Updated 2 weeks ago
- A proof-of-concept, Rust-inspired, declarative hardware description language optimized for RTL coding☆22Mar 3, 2025Updated last year
- Deutsch Language Tool Kit☆12Aug 31, 2015Updated 10 years ago
- SystemVerilog package for reading, manipulating, and writing JSON-formatted data☆12Feb 19, 2022Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- This is the Verilog 2005 parser used by VerilogCreator☆15May 19, 2019Updated 6 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆15Mar 2, 2022Updated 4 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Dec 24, 2024Updated last year
- Convert Xilinx FPGA bitstream from the .bit format (as generated by Vivado) into the .bin format (as expected by Linux fpga_manager)☆15Sep 5, 2023Updated 2 years ago
- Artifacts for the SCVP lecture☆12Nov 17, 2021Updated 4 years ago
- 包括同步FIFO（输入输出位宽相同），异步FIFO（输入输出位宽相同），异步FIFO（能实现输出数据位宽是输入数据位宽的1/2或2倍）☆24Nov 7, 2022Updated 3 years ago
- In love with Atalanta☆15Feb 28, 2025Updated last year
- Bazel build rules for compiling Verilog☆22Mar 4, 2024Updated 2 years ago
- Monitor esxi hardware metrics output to json☆12May 11, 2018Updated 7 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Determines the modules declared and instantiated in a SystemVerilog file☆51Sep 23, 2024Updated last year
- Functional Verification of Physical Layer of PCI Express Gen5.0 Graduation Project Using UVM☆28Jul 17, 2025Updated 8 months ago
- Log file scanner used with EDA tools to classify errors and warnings☆12Nov 14, 2022Updated 3 years ago
- Wavious Wlink☆12Oct 28, 2021Updated 4 years ago
- PSSGen: Portable Test and Stimulus Standard DSL Generator☆14Dec 29, 2025Updated 3 months ago
- A tool for making password-protected files☆11Jul 6, 2023Updated 2 years ago
- A concolic testing engine for RISC-V embedded software with support for SystemC peripherals☆27Oct 4, 2023Updated 2 years ago
- Automatically exported from code.google.com/p/eqntott☆15Sep 23, 2015Updated 10 years ago
- Sphinx extension for visual documentation of hardware written in HWT☆12Nov 12, 2025Updated 5 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A TUI signal waveform viewer.☆23Mar 27, 2025Updated last year
- A Xtext based SystemRDL editor with syntax highlighting and context sensitive help☆12Feb 9, 2024Updated 2 years ago
- Verilog generation tool written in Rust☆62Jun 29, 2023Updated 2 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model.☆12Nov 6, 2019Updated 6 years ago
- Hardware Design, Exploration, and Code Generation for SoC Designers☆12Dec 15, 2019Updated 6 years ago
- Debuggable hardware generator☆71Feb 17, 2023Updated 3 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- SystemVerilog & Verilog Module I/O parser and printer☆25Jul 25, 2021Updated 4 years ago
- Read-only release history for Verilog-Perl☆14Jan 8, 2015Updated 11 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- ☆12Dec 27, 2022Updated 3 years ago
- ☆11Apr 25, 2020Updated 5 years ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆471Mar 30, 2026Updated 2 weeks ago
- Useful UVM extensions☆27Jul 10, 2024Updated last year
- 🚀 LLM inference optimization simulator, modeling compute-bound prefill and memory-bound decode phases.☆14Jul 12, 2025Updated 9 months ago
- ☆14Jun 7, 2021Updated 4 years ago
- Source code for LEF/DEF☆11Oct 16, 2018Updated 7 years ago