Alternatives and similar repositories for py-hpi

Users that are interested in py-hpi are comparing it to the libraries listed below

• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆18Updated 2 years ago
• pybfms / pybfms
  Provides automation scripts for building BFMs
  ☆16Updated 9 months ago
• SymbiFlow / sphinx-verilog-domain
  Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
  ☆26Updated 4 years ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆41Updated 2 months ago
• wallento / cocotbext-uart
  UART cocotb module
  ☆11Updated 4 years ago
• ben-marshall / verilog-doc
  A basic documentation generator for Verilog, similar to Doxygen.
  ☆13Updated 9 years ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 7 years ago
• amiq-consulting / fc4sc
  A header only C++11 library for functional coverage
  ☆36Updated 3 years ago
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆37Updated 3 months ago
• jg-fossh / uvm-python-verification-lib
  UVM Python Verification Agents Library
  ☆15Updated 4 years ago
• Mochenx / sv_csv_parser
  A CSV file parser, written in SystemVerilog
  ☆27Updated 9 years ago
• SpinalHDL / CocotbLib
  ☆18Updated 7 months ago
• amiq-consulting / uvm_reg_to_ipxact
  ☆16Updated 6 years ago
• JoseIuri / UVM_Python
  This repository contains an example of the connection between an UVM Testbench and a Python reference model.
  ☆12Updated 6 years ago
• fvutils / pyucis
  Python API to Unified Coverage Interoperability Standard (UCIS) Data
  ☆29Updated 3 months ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆29Updated 3 years ago
• ZipCPU / axidmacheck
  AXI DMA Check: A utility to measure DMA speeds in simulation
  ☆15Updated last year
• jkorinth / chisel-packaging
  IPXACT packaging utilities for Chisel 3.x using Xilinx Vivado Design Suite.
  ☆11Updated 7 years ago
• tudortimi / ipxact
  IP-XACT XML binding library
  ☆16Updated 9 years ago
• Risto97 / systemc_uvm_verilator
  ☆13Updated 3 years ago
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆47Updated 2 weeks ago
• JoseIuri / UVM_Python_UVMC
  This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…
  ☆17Updated 5 years ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆17Updated 2 weeks ago
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆14Updated last year
• Risto97 / VeriSC
  SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions
  ☆21Updated last year
• ganeshgore / spydrnet-physical
  This is a SpyDrNet Plugin for a physical design related transformations
  ☆16Updated 7 months ago
• taichi-ishitani / rggen
  This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
  ☆17Updated 6 years ago
• ezchi / uvm-systemc
  My local copy of UVM-SystemC
  ☆14Updated last year
• vlotnik / uvm_modem
  UVM components for DSP tasks (MODulation/DEModulation)
  ☆14Updated 3 years ago
• edaa-org / pyEDAA.UCIS
  Unified Coverage Interoperability Standard (UCIS)
  ☆14Updated last week