Alternatives and similar repositories for py-hpi:

Users that are interested in py-hpi are comparing it to the libraries listed below

• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• jg-fossh / uvm-python-verification-lib
  UVM Python Verification Agents Library
  ☆14Updated 4 years ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 6 years ago
• pybfms / pybfms
  Provides automation scripts for building BFMs
  ☆16Updated 3 years ago
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆31Updated last month
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆12Updated 2 months ago
• SymbiFlow / sphinx-verilog-domain
  Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
  ☆23Updated 4 years ago
• fvutils / pyucis
  Python API to Unified Coverage Interoperability Standard (UCIS) Data
  ☆24Updated last month
• RoaLogic / ahb3lite_pkg
  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  ☆17Updated 11 months ago
• tudortimi / ipxact
  IP-XACT XML binding library
  ☆15Updated 8 years ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆36Updated this week
• ZipCPU / axidmacheck
  AXI DMA Check: A utility to measure DMA speeds in simulation
  ☆14Updated 2 months ago
• Inkub / SV-assertions-IF-generator
  Generates a SystemVerilog assertion interface for a given SV RTL design
  ☆15Updated 3 weeks ago
• amiq-consulting / uvm_reg_to_ipxact
  ☆15Updated 5 years ago
• vlotnik / uvm_modem
  UVM components for DSP tasks (MODulation/DEModulation)
  ☆14Updated 3 years ago
• Risto97 / systemc_uvm_verilator
  ☆12Updated 2 years ago
• dpretet / svlogger
  SystemVerilog Logger
  ☆17Updated 2 years ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆37Updated 2 years ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 3 months ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• rggen / rggen-systemverilog
  SystemVerilog RTL and UVM RAL model generators for RgGen
  ☆14Updated last month
• Doulos / SystemC-Engine
  Explore the behavior SystemC kernel event-driven simulator (aka "the engine")
  ☆11Updated last year
• taichi-ishitani / rggen
  This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
  ☆17Updated 5 years ago
• amiq-consulting / amiq_ofc
  Open-Source Framework for Co-Emulation
  ☆11Updated 4 years ago
• taichi-ishitani / tue
  Useful UVM extensions
  ☆21Updated 9 months ago
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆34Updated 6 months ago
• sgherbst / pysvinst
  Python library for parsing module definitions and instantiations from SystemVerilog files
  ☆22Updated 3 years ago
• rggen / rggen-sample-testbench
  ☆14Updated 2 weeks ago
• habibagamal / SoC_Automation
  SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …
  ☆38Updated 4 years ago
• ben-marshall / verilog-doc
  A basic documentation generator for Verilog, similar to Doxygen.
  ☆11Updated 8 years ago