Alternatives and similar repositories for py-hpi

Users that are interested in py-hpi are comparing it to the libraries listed below

• SymbiFlow / sphinx-verilog-domain
  Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
  ☆25Updated 4 years ago
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• pybfms / pybfms
  Provides automation scripts for building BFMs
  ☆16Updated 3 months ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 6 years ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆39Updated last week
• fvutils / pyucis
  Python API to Unified Coverage Interoperability Standard (UCIS) Data
  ☆26Updated 5 months ago
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆35Updated last month
• ben-marshall / verilog-doc
  A basic documentation generator for Verilog, similar to Doxygen.
  ☆12Updated 9 years ago
• amiq-consulting / fc4sc
  A header only C++11 library for functional coverage
  ☆36Updated 2 years ago
• SpinalHDL / CocotbLib
  ☆17Updated 3 weeks ago
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆34Updated this week
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆27Updated 3 years ago
• tudortimi / ipxact
  IP-XACT XML binding library
  ☆16Updated 9 years ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆16Updated last week
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆52Updated last year
• jg-fossh / uvm-python-verification-lib
  UVM Python Verification Agents Library
  ☆14Updated 4 years ago
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆15Updated 6 months ago
• Risto97 / systemc_uvm_verilator
  ☆12Updated 2 years ago
• amiq-consulting / uvm_reg_to_ipxact
  ☆15Updated 6 years ago
• jkorinth / chisel-packaging
  IPXACT packaging utilities for Chisel 3.x using Xilinx Vivado Design Suite.
  ☆11Updated 6 years ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 3 months ago
• SymbioticEDA / sva-demos
  SVA examples and demonstration
  ☆16Updated 4 years ago
• RoaLogic / ahb3lite_pkg
  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  ☆17Updated last year
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆13Updated 2 months ago
• taichi-ishitani / rggen
  This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
  ☆17Updated 6 years ago
• rggen / rggen-systemverilog
  SystemVerilog RTL and UVM RAL model generators for RgGen
  ☆14Updated 2 weeks ago
• vsdip / vsdStdCellCharacterizer_sky130
  ☆20Updated 3 years ago
• vlotnik / uvm_modem
  UVM components for DSP tasks (MODulation/DEModulation)
  ☆14Updated 3 years ago
• tudortimi / vpi
  SystemVerilog wrapper over the Verilog Programming Interface (VPI)
  ☆13Updated 2 months ago
• Minres / RDL-Editor
  A Xtext based SystemRDL editor with syntax highlighting and context sensitive help
  ☆12Updated last year