Alternatives and similar repositories for py-hpi:

Users that are interested in py-hpi are comparing it to the libraries listed below

• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• jg-fossh / uvm-python-verification-lib
  UVM Python Verification Agents Library
  ☆14Updated 3 years ago
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆12Updated last week
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆36Updated this week
• amiq-consulting / uvm_reg_to_ipxact
  ☆15Updated 5 years ago
• fvutils / pyucis
  Python API to Unified Coverage Interoperability Standard (UCIS) Data
  ☆22Updated 4 months ago
• pybfms / pybfms
  Provides automation scripts for building BFMs
  ☆16Updated 3 years ago
• tudortimi / ipxact
  IP-XACT XML binding library
  ☆15Updated 8 years ago
• dpretet / svlogger
  SystemVerilog Logger
  ☆17Updated 2 years ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 6 years ago
• SpinalHDL / CocotbLib
  ☆15Updated last year
• ZipCPU / axidmacheck
  AXI DMA Check: A utility to measure DMA speeds in simulation
  ☆12Updated 3 weeks ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆29Updated last month
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆30Updated this week
• RoaLogic / ahb3lite_pkg
  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  ☆16Updated 9 months ago
• pulp-platform / axi2apb
  ☆18Updated 4 years ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆29Updated 8 years ago
• amiq-consulting / fc4sc
  A header only C++11 library for functional coverage
  ☆36Updated 2 years ago
• ben-marshall / verilog-doc
  A basic documentation generator for Verilog, similar to Doxygen.
  ☆11Updated 8 years ago
• SymbiFlow / sphinx-verilog-domain
  Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
  ☆22Updated 3 years ago
• taichi-ishitani / tue
  Useful UVM extensions
  ☆21Updated 7 months ago
• vlotnik / uvm_modem
  UVM components for DSP tasks (MODulation/DEModulation)
  ☆14Updated 2 years ago
• AsFigo / apb_uvc_verilator
  APB UVC ported to Verilator
  ☆11Updated last year
• go2uvm / go2uvm
  Main repo for Go2UVM source code, examples and apps
  ☆20Updated last year
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• maltanar / systemc-chisel-tools
  A collection of tools for working with Chisel-generated hardware in SystemC
  ☆16Updated 5 years ago
• Risto97 / systemc_uvm_verilator
  ☆11Updated 2 years ago
• SymbioticEDA / sva-demos
  SVA examples and demonstration
  ☆16Updated 4 years ago
• drom / sta
  🕒 Static Timing Analysis diagram renderer
  ☆13Updated last year
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆33Updated 4 months ago