Alternatives and similar repositories for py-hpi

Users that are interested in py-hpi are comparing it to the libraries listed below

• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 6 years ago
• amiq-consulting / fc4sc
  A header only C++11 library for functional coverage
  ☆36Updated 2 years ago
• pybfms / pybfms
  Provides automation scripts for building BFMs
  ☆16Updated 2 months ago
• tudortimi / ipxact
  IP-XACT XML binding library
  ☆16Updated 9 years ago
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆35Updated 3 weeks ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆39Updated this week
• jg-fossh / uvm-python-verification-lib
  UVM Python Verification Agents Library
  ☆14Updated 4 years ago
• SymbiFlow / sphinx-verilog-domain
  Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
  ☆25Updated 4 years ago
• fvutils / pyucis
  Python API to Unified Coverage Interoperability Standard (UCIS) Data
  ☆26Updated 4 months ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆70Updated last month
• oddball / ipxact2systemverilog
  Translates IPXACT XML to synthesizable VHDL or SystemVerilog
  ☆61Updated 2 weeks ago
• amiq-consulting / uvm_reg_to_ipxact
  ☆15Updated 6 years ago
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆34Updated last month
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆27Updated 3 years ago
• tudortimi / vpi
  SystemVerilog wrapper over the Verilog Programming Interface (VPI)
  ☆13Updated last month
• Inkub / SV-assertions-IF-generator
  Generates a SystemVerilog assertion interface for a given SV RTL design
  ☆18Updated 3 months ago
• taichi-ishitani / rggen
  This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
  ☆17Updated 5 years ago
• JoseIuri / UVM_Python
  This repository contains an example of the connection between an UVM Testbench and a Python reference model.
  ☆10Updated 5 years ago
• SpinalHDL / CocotbLib
  ☆17Updated this week
• amiq-consulting / amiq_blog
  Code snippets from articles published on www.amiq.com/consulting/blog
  ☆36Updated last year
• JoseIuri / UVM_Python_UVMC
  This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…
  ☆16Updated 5 years ago
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆13Updated last month
• taichi-ishitani / tue
  Useful UVM extensions
  ☆24Updated last year
• rggen / rggen-systemverilog
  SystemVerilog RTL and UVM RAL model generators for RgGen
  ☆14Updated last month
• ben-marshall / verilog-doc
  A basic documentation generator for Verilog, similar to Doxygen.
  ☆12Updated 8 years ago
• go2uvm / go2uvm
  Main repo for Go2UVM source code, examples and apps
  ☆21Updated 2 years ago
• funningboy / pyvpi_example
  use pivpi to drive testbench event
  ☆21Updated 8 years ago
• RoaLogic / ahb3lite_pkg
  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  ☆17Updated last year
• vlotnik / uvm_modem
  UVM components for DSP tasks (MODulation/DEModulation)
  ☆14Updated 3 years ago