vegaluisjose / vastLinks
Verilog AST
☆21Updated 2 years ago
Alternatives and similar repositories for vast
Users that are interested in vast are comparing it to the libraries listed below
Sorting:
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated 2 years ago
- ☆40Updated 4 years ago
- A Hardware Pipeline Description Language☆49Updated 6 months ago
- The PE for the second generation CGRA (garnet).☆18Updated 8 months ago
- Fast PnR toolchain for CGRA☆18Updated last year
- RTLCheck☆24Updated 7 years ago
- 21st century electronic design automation tools, written in Rust.☆33Updated last week
- A Coq framework to support structural design and proof of hardware cache-coherence protocols☆14Updated 3 years ago
- ☆104Updated 3 years ago
- BTOR2 MLIR project☆26Updated last year
- Logic circuit analysis and optimization☆45Updated 4 months ago
- FPGA synthesis tool powered by program synthesis☆54Updated 3 weeks ago
- Verilator Porcelain☆49Updated 2 years ago
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 4 years ago
- Time-sensitive affine types for predictable hardware generation☆148Updated last week
- ☆13Updated 4 years ago
- ☆19Updated last year
- ☆30Updated 3 years ago
- Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics☆18Updated 2 years ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆34Updated 11 months ago
- CoreIR Symbolic Analyzer☆74Updated 5 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Updated 5 years ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆37Updated this week
- Peak : Processor Specification Language ala Newell and Bell's ISP☆20Updated 2 years ago
- Debuggable hardware generator☆70Updated 2 years ago
- Testing processors with Random Instruction Generation☆50Updated last month
- design and verification of asynchronous circuits☆42Updated 3 weeks ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Updated 3 years ago
- A Verilog Filelist parser in Rust☆11Updated 3 years ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆33Updated last week