Alternatives and similar repositories for vast

Users that are interested in vast are comparing it to the libraries listed below

• mikeurbach / egg-netlist-synthesizer
  Using e-graphs to synthesize netlists from boolean logic.
  ☆14Updated 2 years ago
• ucb-substrate / substrate2
  21st century electronic design automation tools, written in Rust.
  ☆33Updated this week
• vegaluisjose / reticle
  ☆40Updated 4 years ago
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆49Updated 5 months ago
• ymanerka / rtlcheck
  RTLCheck
  ☆23Updated 7 years ago
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated 8 months ago
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆26Updated last year
• Kuree / cgra_pnr
  Fast PnR toolchain for CGRA
  ☆18Updated last year
• Coloquinte / quaigh
  Logic circuit analysis and optimization
  ☆45Updated 4 months ago
• rdaly525 / coreir
  ☆104Updated 3 years ago
• upscale-project / generic-sqed-demo
  ☆13Updated 4 years ago
• mit-plv / hemiola
  A Coq framework to support structural design and proof of hardware cache-coherence protocols
  ☆14Updated 3 years ago
• leonardt / hwtypes
  Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics
  ☆18Updated 2 years ago
• iscas-tis / CHA
  ☆19Updated last year
• pku-liang / Cement
  The Next-gen Language & Compiler Powering Efficient Hardware Design
  ☆34Updated 11 months ago
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆33Updated 4 months ago
• comsec-group / cellift-yosys
  A fork of Yosys that integrates the CellIFT pass
  ☆13Updated 5 months ago
• gussmith23 / lakeroad
  FPGA synthesis tool powered by program synthesis
  ☆53Updated last week
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆116Updated 7 months ago
• cucapra / latte21
  Languages, Tools, and Techniques for Accelerator Design
  ☆33Updated 4 years ago
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆50Updated last month
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆38Updated 4 years ago
• Lampro-Mellon / Quasar
  Quasar 2.0: Chisel equivalent of SweRV-EL2
  ☆31Updated 4 years ago
• B-Lang-org / bsc-contrib
  A place to share libraries and utilities that don't belong in the core bsc repo
  ☆37Updated last month
• Raamakrishnan / verilog-filelist-parser
  A Verilog Filelist parser in Rust
  ☆11Updated 3 years ago
• gokhankici / iodine
  Iodine: Verifying Constant-Time Execution of Hardware
  ☆15Updated 4 years ago
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆19Updated 3 years ago
• chipsalliance / fpga-interchange-schema
  ☆59Updated 3 years ago
• calyxir / calyx-riscv
  RISCV Core written in Calyx
  ☆17Updated last year
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆74Updated 5 years ago