vegaluisjose / vastLinks
Verilog AST
☆21Updated last year
Alternatives and similar repositories for vast
Users that are interested in vast are comparing it to the libraries listed below
Sorting:
- A Hardware Pipeline Description Language☆45Updated 3 weeks ago
- ☆40Updated 3 years ago
- 21st century electronic design automation tools, written in Rust.☆31Updated 3 weeks ago
- The PE for the second generation CGRA (garnet).☆17Updated 3 months ago
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated 2 years ago
- Fast PnR toolchain for CGRA☆18Updated last year
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 3 years ago
- Logic circuit analysis and optimization☆43Updated 3 weeks ago
- ☆103Updated 3 years ago
- RTLCheck☆22Updated 6 years ago
- FPGA synthesis tool powered by program synthesis☆51Updated 3 weeks ago
- Time-sensitive affine types for predictable hardware generation☆145Updated 3 weeks ago
- Verilator Porcelain☆48Updated last year
- ☆56Updated 3 years ago
- Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics☆18Updated last year
- A Coq framework to support structural design and proof of hardware cache-coherence protocols☆14Updated 3 years ago
- BTOR2 MLIR project☆26Updated last year
- design and verification of asynchronous circuits☆39Updated last week
- CoreIR Symbolic Analyzer☆73Updated 4 years ago
- RISCV Core written in Calyx☆17Updated 11 months ago
- Chisel library for Unum Type-III Posit Arithmetic☆39Updated 4 months ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 3 years ago
- Debuggable hardware generator☆69Updated 2 years ago
- Hardware generator debugger☆74Updated last year
- A place to share libraries and utilities that don't belong in the core bsc repo☆36Updated 4 months ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆36Updated 4 years ago
- Papers, Posters, Presentations, Documentation...☆19Updated last year
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆145Updated 2 months ago
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Updated 2 years ago