uwplse / rakeLinks
compiling DSLs to high-level hardware instructions
☆22Updated 2 years ago
Alternatives and similar repositories for rake
Users that are interested in rake are comparing it to the libraries listed below
Sorting:
- Bridging polyhedral analysis tools to the MLIR framework☆113Updated last year
- Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification☆15Updated 7 months ago
- FPGA synthesis tool powered by program synthesis☆51Updated last week
- PolyGen is a code generator for the polyhedral model, written and proved in Coq.☆10Updated 4 years ago
- ☆30Updated 2 years ago
- A translation validation framework for MLIR☆87Updated 3 months ago
- BTOR2 MLIR project☆26Updated last year
- ☆40Updated 3 years ago
- A formalization of the RVWMO (RISC-V) memory model☆34Updated 3 years ago
- Asynchronous semantics for architectural simulation and synthesis.☆39Updated this week
- A pure, low-level tensor program representation enabling tensor program optimization via program rewriting. See the web demo at https://g…☆70Updated last month
- HeteroCL-MLIR dialect for accelerator design☆41Updated 9 months ago
- A Speculation-Aware Collaborative Dependence Analysis Framework☆28Updated last year
- Polyhedral High-Level Synthesis in MLIR☆33Updated 2 years ago
- A Hardware Pipeline Description Language☆45Updated last year
- RTLCheck☆22Updated 6 years ago
- Code released to accompany the ISCA paper: "T4: Compiling Sequential Code for Effective Speculative Parallelization in Hardware"☆28Updated 3 years ago
- A enumerator for MLIR, relying on the information given by IRDL.☆19Updated this week
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆29Updated 5 months ago
- Website for CS 265☆29Updated 6 months ago
- Verilog AST☆21Updated last year
- A retargetable and extensible synthesis-based compiler for modern hardware architectures☆12Updated 2 months ago
- Updated C version of the Test Suite for Vectorising Compilers☆63Updated last year
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆22Updated last year
- ☆19Updated last year
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 3 years ago
- Optimizing scheduler. Combinatorial instruction scheduling project.☆26Updated 3 weeks ago
- An out-of-tree MLIR dialect template.☆103Updated 10 months ago
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated last year
- The Splash-3 benchmark suite☆44Updated 2 years ago