uwplse / rakeLinks
compiling DSLs to high-level hardware instructions
☆23Updated 2 years ago
Alternatives and similar repositories for rake
Users that are interested in rake are comparing it to the libraries listed below
Sorting:
- Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification☆15Updated last week
- Bridging polyhedral analysis tools to the MLIR framework☆116Updated 2 years ago
- A translation validation framework for MLIR☆87Updated 5 months ago
- BTOR2 MLIR project☆26Updated last year
- ☆31Updated 2 years ago
- FPGA synthesis tool powered by program synthesis☆52Updated 2 months ago
- A Hardware Pipeline Description Language☆45Updated 2 months ago
- ☆40Updated 3 years ago
- A pure, low-level tensor program representation enabling tensor program optimization via program rewriting. See the web demo at https://g…☆70Updated 3 months ago
- Polyhedral High-Level Synthesis in MLIR☆33Updated 2 years ago
- HeteroCL-MLIR dialect for accelerator design☆41Updated 11 months ago
- A toy compiler for NumPy array expressions that uses e-graphs and MLIR☆105Updated last month
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆29Updated 7 months ago
- Code released to accompany the ISCA paper: "T4: Compiling Sequential Code for Effective Speculative Parallelization in Hardware"☆28Updated 3 years ago
- Verilog AST☆21Updated last year
- A formalization of the RVWMO (RISC-V) memory model☆35Updated 3 years ago
- Website for CS 265☆29Updated 8 months ago
- Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)☆31Updated last year
- ☆19Updated last year
- Time-sensitive affine types for predictable hardware generation☆145Updated this week
- A Coq framework to support structural design and proof of hardware cache-coherence protocols☆14Updated 3 years ago
- Memory consistency modelling using Alloy☆31Updated 4 years ago
- ☆40Updated this week
- Optimizing scheduler. Combinatorial instruction scheduling project.☆26Updated 2 months ago
- A retargetable and extensible synthesis-based compiler for modern hardware architectures☆13Updated 4 months ago
- The CLooG Code Generator in the Polyhedral Model☆51Updated 2 years ago
- A Speculation-Aware Collaborative Dependence Analysis Framework☆28Updated last year
- Example for running IREE in a bare-metal Arm environment.☆40Updated last month
- RTLCheck☆22Updated 6 years ago
- A polyhedral compiler for hardware accelerators☆59Updated last year