uwplse / rakeLinks
compiling DSLs to high-level hardware instructions
☆23Updated 2 years ago
Alternatives and similar repositories for rake
Users that are interested in rake are comparing it to the libraries listed below
Sorting:
- FPGA synthesis tool powered by program synthesis☆51Updated 3 weeks ago
- Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification☆15Updated 8 months ago
- A translation validation framework for MLIR☆88Updated 4 months ago
- Bridging polyhedral analysis tools to the MLIR framework☆116Updated last year
- ☆30Updated 2 years ago
- BTOR2 MLIR project☆26Updated last year
- A Hardware Pipeline Description Language☆45Updated 3 weeks ago
- Verilog AST☆21Updated last year
- ☆40Updated 3 years ago
- A pure, low-level tensor program representation enabling tensor program optimization via program rewriting. See the web demo at https://g…☆70Updated 2 months ago
- A enumerator for MLIR, relying on the information given by IRDL.☆19Updated 3 weeks ago
- HeteroCL-MLIR dialect for accelerator design☆41Updated 10 months ago
- RTLCheck☆22Updated 6 years ago
- Time-sensitive affine types for predictable hardware generation☆145Updated 3 weeks ago
- Polyhedral High-Level Synthesis in MLIR☆33Updated 2 years ago
- ☆19Updated last year
- Asynchronous semantics for architectural simulation and synthesis.☆40Updated 2 weeks ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆30Updated 5 months ago
- Code released to accompany the ISCA paper: "T4: Compiling Sequential Code for Effective Speculative Parallelization in Hardware"☆29Updated 3 years ago
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 3 years ago
- A formalization of the RVWMO (RISC-V) memory model☆34Updated 3 years ago
- A polyhedral compiler for hardware accelerators☆59Updated last year
- A Coq framework to support structural design and proof of hardware cache-coherence protocols☆14Updated 3 years ago
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated 2 years ago
- CoreIR Symbolic Analyzer☆73Updated 4 years ago
- A Speculation-Aware Collaborative Dependence Analysis Framework☆28Updated last year
- Website for CS 265☆29Updated 7 months ago
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆23Updated last year
- Example for running IREE in a bare-metal Arm environment.☆38Updated this week
- Microarchitecture diagrams of several CPUs☆37Updated 3 weeks ago