uwplse / rake

Related projects ⓘ

Alternatives and complementary repositories for rake

• gussmith23 / lakeroad
  FPGA synthesis tool powered by program synthesis
  ☆38Updated this week
• ychen306 / vegen
  ☆27Updated last year
• Ekdohibs / PolyGen
  PolyGen is a code generator for the polyhedral model, written and proved in Coq.
  ☆10Updated 4 years ago
• aqjune / mlir-tv
  A translation validation framework for MLIR
  ☆73Updated last week
• kumasento / polsca
  Polyhedral High-Level Synthesis in MLIR
  ☆29Updated last year
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆40Updated last year
• kumasento / polymer
  Bridging polyhedral analysis tools to the MLIR framework
  ☆102Updated last year
• SwarmArch / T4
  Code released to accompany the ISCA paper: "T4: Compiling Sequential Code for Effective Speculative Parallelization in Hardware"
  ☆27Updated 2 years ago
• were / bfsh
  Being a full-stack hacker, RISCV, LLVM, and more.
  ☆18Updated 3 years ago
• PrincetonUniversity / SCAF
  A Speculation-Aware Collaborative Dependence Analysis Framework
  ☆28Updated 4 months ago
• cornell-zhang / hcl-dialect
  HeteroCL-MLIR dialect for accelerator design
  ☆40Updated 2 months ago
• johnwickerson / memalloy
  Memory consistency modelling using Alloy
  ☆28Updated 3 years ago
• pnnl / COMET
  ☆37Updated this week
• vegaluisjose / reticle
  ☆41Updated 3 years ago
• vegaluisjose / vast
  Verilog AST
  ☆19Updated 11 months ago
• NVlabs / litmustestgen
  Alloy models for automatic synthesis of memory model litmus test suites (from ASPLOS 2017)
  ☆15Updated 9 months ago
• sgpthomas / comp-gen
  Automatically generate a compiler using equality saturation
  ☆26Updated 7 months ago
• iscas-tis / CHA
  ☆14Updated 4 months ago
• yihozhang / relational-ematching-benchmark
  ☆15Updated 2 years ago
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆55Updated last week
• cucapra / latte21
  Languages, Tools, and Techniques for Accelerator Design
  ☆33Updated 3 years ago
• gussmith23 / glenside
  A pure, low-level tensor program representation enabling tensor program optimization via program rewriting. See the web demo at https://g…
  ☆71Updated 5 months ago
• gokhankici / iodine
  Iodine: Verifying Constant-Time Execution of Hardware
  ☆11Updated 3 years ago
• sderek / CUDAAdvisor
  CUDAAdvisor: a GPU profiling tool
  ☆48Updated 6 years ago
• PrincetonUniversity / IMDb-Archive
  ILA Model Database
  ☆20Updated 4 years ago
• akothen / Hydride
  A retargetable and extensible synthesis-based compiler for modern hardware architectures
  ☆10Updated last week
• daniellustig / riscv-memory-model
  A formalization of the RVWMO (RISC-V) memory model
  ☆30Updated 2 years ago
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆16Updated 10 months ago
• iree-org / iree-bare-metal-arm
  Example for running IREE in a bare-metal Arm environment.
  ☆23Updated 2 months ago
• sifive / chisel-circt
  Library to compile Chisel circuits using LLVM/MLIR (CIRCT)
  ☆70Updated last year