The SiFive wake build tool
☆94Sep 4, 2026Updated this week
Alternatives and similar repositories for wake
Users that are interested in wake are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Workspace Integration Tool☆23Nov 6, 2020Updated 5 years ago
- An example of on-boarding a PIO block in with duh and wake☆12Nov 18, 2020Updated 5 years ago
- Wake build descriptions of hardware generators☆12Dec 11, 2020Updated 5 years ago
- 👾 Design ∪ Hardware☆79Jul 1, 2026Updated 2 months ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆84Jun 1, 2022Updated 4 years ago
- ☆17Mar 17, 2022Updated 4 years ago
- Hardware generator debugger☆79Feb 12, 2024Updated 2 years ago
- A stream to RTL compiler based on MLIR and CIRCT☆17Nov 15, 2022Updated 3 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Sep 30, 2020Updated 5 years ago
- Tools based upon slang for language server purpose☆24Updated this week
- Library to compile Chisel circuits using LLVM/MLIR (CIRCT)☆70Mar 2, 2023Updated 3 years ago
- A Library of Chisel3 Tools for Digital Signal Processing☆250Apr 29, 2024Updated 2 years ago
- For contributions of Chisel IP to the chisel community.☆73Nov 7, 2024Updated last year
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- The 'missing header' for Chisel☆24Feb 5, 2026Updated 7 months ago
- high-performance RTL simulator☆195Aug 4, 2026Updated last month
- Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (htt…☆168Aug 25, 2026Updated last week
- Flexible Intermediate Representation for RTL☆747Aug 20, 2024Updated 2 years ago
- ☆13Feb 13, 2021Updated 5 years ago
- Sticky sticky PCI☆10Oct 25, 2018Updated 7 years ago
- RISC-V CPU in SystemVerilog & Custom Migen-based SoC Generator☆11Dec 29, 2021Updated 4 years ago
- Wrappers for open source FPU hardware implementations.☆37Nov 27, 2025Updated 9 months ago
- Models of finite automata (DFA, NFA) with support of common operations and easily readable creation of objects☆14Feb 4, 2019Updated 7 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Checkpoint 401 Forward Auth Security Server.☆17Apr 25, 2026Updated 4 months ago
- ☆37Mar 20, 2025Updated last year
- A minimal in MLIR dialect along the lines of STG to represent laziness.☆17Jan 7, 2022Updated 4 years ago
- Simple MIDAS Examples☆12Nov 25, 2018Updated 7 years ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆301Updated this week
- The specification for the FIRRTL language☆67Updated this week
- A Verilog Filelist parser in Rust☆11Mar 25, 2022Updated 4 years ago
- Open source hardware down to the chip level!☆30Sep 24, 2021Updated 4 years ago
- Converting systemverilog to verilog.☆10Feb 15, 2018Updated 8 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Chisel/Firrtl execution engine☆157Aug 21, 2024Updated 2 years ago
- what is the soul of man when soul and body seperates body dies soul lives fear not man which can only destroy the body, but fear him whic…☆21Aug 14, 2013Updated 13 years ago
- Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.☆34Feb 6, 2020Updated 6 years ago
- Chisel3 AXI4-{Lite, Full, Stream} Definitions☆15Dec 31, 2018Updated 7 years ago
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Jul 23, 2019Updated 7 years ago
- Bitcoin full node as a C Programming Language library☆10Dec 3, 2025Updated 9 months ago
- Block-diagram style digital logic visualizer☆23Sep 16, 2015Updated 10 years ago