The SiFive wake build tool
☆94Sep 24, 2026Updated this week
Alternatives and similar repositories for wake
Users that are interested in wake are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Workspace Integration Tool☆23Nov 6, 2020Updated 5 years ago
- An example of on-boarding a PIO block in with duh and wake☆12Nov 18, 2020Updated 5 years ago
- 👾 Design ∪ Hardware☆79Sep 17, 2026Updated last week
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- ☆84Jun 1, 2022Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆17Mar 17, 2022Updated 4 years ago
- Hardware generator debugger☆79Feb 12, 2024Updated 2 years ago
- A stream to RTL compiler based on MLIR and CIRCT☆17Nov 15, 2022Updated 3 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Sep 30, 2020Updated 5 years ago
- Tools based upon slang for language server purpose☆24Sep 10, 2026Updated 2 weeks ago
- Library to compile Chisel circuits using LLVM/MLIR (CIRCT)☆70Mar 2, 2023Updated 3 years ago
- A Library of Chisel3 Tools for Digital Signal Processing☆250Apr 29, 2024Updated 2 years ago
- For contributions of Chisel IP to the chisel community.☆73Sep 17, 2026Updated last week
- The 'missing header' for Chisel☆24Feb 5, 2026Updated 7 months ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- high-performance RTL simulator☆196Aug 4, 2026Updated last month
- Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (htt…☆169Updated this week
- Flexible Intermediate Representation for RTL☆746Aug 20, 2024Updated 2 years ago
- Sticky sticky PCI☆10Oct 25, 2018Updated 7 years ago
- Using e-graphs to synthesize netlists from boolean logic.☆14Jul 26, 2023Updated 3 years ago
- RISC-V CPU in SystemVerilog & Custom Migen-based SoC Generator☆11Dec 29, 2021Updated 4 years ago
- Models of finite automata (DFA, NFA) with support of common operations and easily readable creation of objects☆14Feb 4, 2019Updated 7 years ago
- Checkpoint 401 Forward Auth Security Server.☆17Apr 25, 2026Updated 5 months ago
- ☆37Mar 20, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆234Aug 19, 2024Updated 2 years ago
- A minimal in MLIR dialect along the lines of STG to represent laziness.☆17Jan 7, 2022Updated 4 years ago
- Simple MIDAS Examples☆12Nov 25, 2018Updated 7 years ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆302Sep 2, 2026Updated 3 weeks ago
- The specification for the FIRRTL language☆67Updated this week
- A Verilog Filelist parser in Rust☆11Mar 25, 2022Updated 4 years ago
- Converting systemverilog to verilog.☆10Feb 15, 2018Updated 8 years ago
- Chisel/Firrtl execution engine☆157Aug 21, 2024Updated 2 years ago
- what is the soul of man when soul and body seperates body dies soul lives fear not man which can only destroy the body, but fear him whic…☆21Aug 14, 2013Updated 13 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Bazel build rules for Verilator☆24Apr 4, 2024Updated 2 years ago
- Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.☆34Feb 6, 2020Updated 6 years ago
- Chisel3 AXI4-{Lite, Full, Stream} Definitions☆15Dec 31, 2018Updated 7 years ago
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Jul 23, 2019Updated 7 years ago
- Bitcoin full node as a C Programming Language library☆10Dec 3, 2025Updated 9 months ago
- Block-diagram style digital logic visualizer☆23Sep 16, 2015Updated 11 years ago
- Provides dot visualizations of chisel/firrtl circuites☆13Mar 12, 2019Updated 7 years ago