Alternatives and similar repositories for wake

Users that are interested in wake are comparing it to the libraries listed below

• riscv / riscv-j-extension
  Working Draft of the RISC-V J Extension Specification
  ☆191Updated 3 weeks ago
• riscvarchive / riscv-code-size-reduction
  ☆147Updated last year
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆97Updated 3 years ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆62Updated last week
• riscv-admin / riscv-ovpsim
  ☆61Updated 4 years ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆149Updated 2 weeks ago
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆215Updated last year
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆101Updated 5 years ago
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆226Updated last year
• ArchC / ArchC
  A powerful and modern open-source architecture description language.
  ☆44Updated 8 years ago
• microsoft / cheriot-ibex
  cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
  ☆113Updated 2 months ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆161Updated 3 years ago
• cucapra / dahlia
  Time-sensitive affine types for predictable hardware generation
  ☆146Updated this week
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆177Updated 6 months ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆273Updated last month
• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆138Updated 2 years ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆235Updated 11 months ago
• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆153Updated last year
• fabianschuiki / moore
  A hardware compiler based on LLHD and CIRCT
  ☆264Updated 4 months ago
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆192Updated this week
• antonblanchard / chiselwatt
  A tiny POWER Open ISA soft processor written in Chisel
  ☆111Updated 2 years ago
• gsmecher / minimax
  Minimax: a Compressed-First, Microcoded RISC-V CPU
  ☆222Updated last year
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆164Updated 5 years ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆37Updated 4 years ago
• pc2 / sus-compiler
  A new Hardware Design Language that keeps you in the driver's seat
  ☆116Updated last week
• riscv / riscv-cheri
  This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory prot…
  ☆85Updated this week
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆150Updated last year
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆151Updated last week
• ucb-bar / berkeley-testfloat-3
  TestFloat release 3
  ☆68Updated 8 months ago
• CTSRD-CHERI / beri
  The BERI and CHERI processor and hardware platform
  ☆49Updated 8 years ago