Alternatives and similar repositories for wake

Users that are interested in wake are comparing it to the libraries listed below

• riscv / riscv-j-extension
  Working Draft of the RISC-V J Extension Specification
  ☆191Updated 2 months ago
• riscvarchive / riscv-code-size-reduction
  ☆147Updated last year
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆180Updated 7 months ago
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆98Updated 3 years ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆151Updated last month
• riscv-admin / riscv-ovpsim
  ☆61Updated 4 years ago
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆227Updated 2 years ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆276Updated 2 months ago
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆216Updated last year
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆236Updated last year
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆168Updated 5 years ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆162Updated 3 years ago
• cucapra / dahlia
  Time-sensitive affine types for predictable hardware generation
  ☆147Updated last month
• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆153Updated last year
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆101Updated 6 years ago
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆153Updated last month
• fabianschuiki / moore
  A hardware compiler based on LLHD and CIRCT
  ☆264Updated 5 months ago
• BSVLang / Main
  Main page
  ☆129Updated 5 years ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆62Updated 2 weeks ago
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆66Updated 5 months ago
• ArchC / ArchC
  A powerful and modern open-source architecture description language.
  ☆46Updated 8 years ago
• B-Lang-org / bsc-contrib
  A place to share libraries and utilities that don't belong in the core bsc repo
  ☆37Updated last month
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆205Updated this week
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆329Updated 3 years ago
• microsoft / cheriot-ibex
  cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
  ☆115Updated 3 months ago
• pc2 / sus-compiler
  A new Hardware Design Language that keeps you in the driver's seat
  ☆118Updated last week
• gsmecher / minimax
  Minimax: a Compressed-First, Microcoded RISC-V CPU
  ☆222Updated last year
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆170Updated this week
• CTSRD-CHERI / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆34Updated this week
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆38Updated 4 years ago