sifiveinc / wake
The SiFive wake build tool
☆90Updated this week
Alternatives and similar repositories for wake:
Users that are interested in wake are comparing it to the libraries listed below
- ☆150Updated last year
- Tile based architecture designed for computing efficiency, scalability and generality☆253Updated this week
- ☆61Updated 4 years ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆151Updated 3 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆141Updated this week
- Time-sensitive affine types for predictable hardware generation☆143Updated 9 months ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆223Updated last year
- Chisel/Firrtl execution engine☆153Updated 8 months ago
- The specification for the FIRRTL language☆54Updated last week
- ☆102Updated 2 years ago
- Hardware generator debugger☆73Updated last year
- RISC-V RV64GC emulator designed for RTL co-simulation☆229Updated 5 months ago
- A hardware compiler based on LLHD and CIRCT☆256Updated last year
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆174Updated 9 months ago
- Working Draft of the RISC-V J Extension Specification☆185Updated this week
- Working draft of the proposed RISC-V Bitmanipulation extension☆210Updated last year
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆145Updated 6 months ago
- RiscyOO: RISC-V Out-of-Order Processor☆156Updated 4 years ago
- Main page☆126Updated 5 years ago
- RISC-V Torture Test☆193Updated 9 months ago
- FPGA Assembly (FASM) Parser and Generator☆91Updated 2 years ago
- (System)Verilog to Chisel translator☆113Updated 2 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 5 years ago
- pulp_soc is the core building component of PULP based SoCs☆79Updated 2 months ago
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆154Updated 2 weeks ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated last year
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆162Updated 3 months ago
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆80Updated 5 months ago
- ☆84Updated this week