Alternatives and similar repositories for WaveDromTikZ

Users that are interested in WaveDromTikZ are comparing it to the libraries listed below

• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆112Updated 4 years ago
• Paebbels / JSON-for-VHDL
  A JSON library implemented in VHDL.
  ☆79Updated 3 years ago
• pieter3d / simview
  ☆87Updated 3 weeks ago
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆97Updated 3 years ago
• yne / vcd
  VCD file (Value Change Dump) command line viewer
  ☆120Updated 2 years ago
• wavedrom / cli
  CLI for WaveDrom
  ☆63Updated last year
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆118Updated 2 years ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆245Updated last year
• GeezerGeek / open_sld
  Direct Python interface to Altera SLD Mega-function
  ☆20Updated 11 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆81Updated 3 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆121Updated last year
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆48Updated 10 months ago
• ldoolitt / vhd2vl
  ☆137Updated 11 months ago
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆80Updated 3 years ago
• cliffordwolf / PonyLink
  A single-wire bi-directional chip-to-chip interface for FPGAs
  ☆123Updated 9 years ago
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆186Updated 3 weeks ago
• hdl / containers
  Building and deploying container images for open source electronic design automation (EDA)
  ☆116Updated last year
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆48Updated 3 years ago
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆117Updated 4 years ago
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 3 years ago
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆21Updated 4 years ago
• ZipCPU / wbscope
  A wishbone controlled scope for FPGA's
  ☆84Updated last year
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆181Updated last week
• ghdl / docker
  Scripts to build and use docker images including GHDL
  ☆43Updated 11 months ago
• olofk / corescore
  CoreScore
  ☆166Updated 2 weeks ago
• VHDL / awesome-vhdl
  A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.
  ☆82Updated 5 years ago
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 3 years ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 9 months ago
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆51Updated this week
• Ravenslofty / blog
  The Critical Path - a rambly FPGA blog
  ☆50Updated 5 years ago