Alternatives and similar repositories for WaveDromTikZ

Users that are interested in WaveDromTikZ are comparing it to the libraries listed below

• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆114Updated 3 years ago
• pieter3d / simview
  ☆79Updated this week
• cliffordwolf / PonyLink
  A single-wire bi-directional chip-to-chip interface for FPGAs
  ☆124Updated 9 years ago
• Kuree / hgdb
  Hardware generator debugger
  ☆75Updated last year
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆117Updated last year
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆48Updated 8 months ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆86Updated 3 weeks ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆245Updated 10 months ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆117Updated last year
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 3 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆78Updated 3 years ago
• ldoolitt / vhd2vl
  ☆136Updated 8 months ago
• yne / vcd
  VCD file (Value Change Dump) command line viewer
  ☆119Updated 2 years ago
• hdl / containers
  Building and deploying container images for open source electronic design automation (EDA)
  ☆116Updated 11 months ago
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆45Updated 3 years ago
• wavedrom / cli
  CLI for WaveDrom
  ☆62Updated last year
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆97Updated 3 years ago
• Paebbels / JSON-for-VHDL
  A JSON library implemented in VHDL.
  ☆79Updated 3 years ago
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆137Updated 3 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆88Updated last month
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆209Updated 5 months ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆155Updated 3 months ago
• VHDL / awesome-vhdl
  A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.
  ☆81Updated 5 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆147Updated 3 months ago
• ZipCPU / vgasim
  A Video display simulator
  ☆171Updated 3 months ago
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆115Updated 4 years ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆50Updated 5 months ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆70Updated 3 years ago
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆49Updated this week
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆181Updated this week