Python script to transform a VCD file to wavedrom format
☆84Aug 18, 2022Updated 3 years ago
Alternatives and similar repositories for vcd2wavedrom
Users that are interested in vcd2wavedrom are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Web-based HDL diagramming tool☆83May 1, 2023Updated 2 years ago
- sample VCD files☆43Feb 13, 2026Updated last month
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 6 years ago
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- Value Change Dump (VCD) parser☆38Jan 9, 2026Updated 2 months ago
- ☆12Jun 4, 2021Updated 4 years ago
- Python Tool for UVM Testbench Generation☆55May 19, 2024Updated last year
- IOb_SoC version of the Picorv32 RISC-V Verilog IP core☆14Dec 22, 2025Updated 3 months ago
- vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.☆26Jan 7, 2016Updated 10 years ago
- Hardware generator debugger☆77Feb 12, 2024Updated 2 years ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- Device description files (architecture, timing, configuration bitstream, and general documentation) for EOS S3 MCU+eFPGA SoC☆27Sep 1, 2021Updated 4 years ago
- wavedrom to verilog converter☆17Sep 14, 2021Updated 4 years ago
- WaveDrom compatible python command line☆114Jun 2, 2023Updated 2 years ago
- FuseSoc Verification Automation☆22Jul 21, 2022Updated 3 years ago
- Example of how to use UVM with Verilator☆39Feb 19, 2026Updated last month
- converts ValueChangeDump-Files (vcd) to tikz-timing-diagrams☆16Nov 19, 2021Updated 4 years ago
- Utilities for Avalon Memory Map☆11Jul 11, 2024Updated last year
- A simple function to add wavedrom diagrams into an ipython notebook.☆24Jan 14, 2022Updated 4 years ago
- Unit testing for cocotb☆169Dec 6, 2025Updated 3 months ago
- A Python package to use FPGA development tools programmatically.☆146Mar 22, 2025Updated last year
- Test suite designed to check compliance with the SystemVerilog standard.☆368Updated this week
- Python package for writing Value Change Dump (VCD) files.☆131Nov 10, 2024Updated last year
- Fixed point package for Python.☆36Apr 28, 2023Updated 2 years ago
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Feb 24, 2026Updated last month
- Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics☆18Sep 13, 2023Updated 2 years ago
- This is an OOT module for GNU Radio integrating verilog simulation feature☆38Sep 23, 2019Updated 6 years ago
- Create WaveJSON from VCD file. WaveDrom can convert it to timing diagram.☆41Jul 24, 2024Updated last year
- A command-line tool for displaying vcd waveforms.☆68Feb 19, 2024Updated 2 years ago
- A flexible and scalable development platform for modern FPGA projects.☆41Mar 16, 2026Updated last week
- CLI for WaveDrom☆69Feb 22, 2024Updated 2 years ago
- Mutation Cover with Yosys (MCY)☆91Mar 4, 2026Updated 2 weeks ago
- ☆12Dec 22, 2020Updated 5 years ago
- Coarse Grained Reconfigurable Array☆20Feb 18, 2026Updated last month
- XC2064 bitstream documentation☆18Sep 24, 2018Updated 7 years ago
- Generic Logic Interfacing Project☆48Jul 29, 2020Updated 5 years ago
- An abstraction library for interfacing EDA tools☆754Mar 11, 2026Updated last week
- SystemVerilog grammar for tree-sitter☆113Nov 11, 2024Updated last year
- A modern hardware definition language and toolchain based on Python☆1,953Mar 16, 2026Updated last week