Python script to transform a VCD file to wavedrom format
☆86Aug 18, 2022Updated 4 years ago
Alternatives and similar repositories for vcd2wavedrom
Users that are interested in vcd2wavedrom are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Web-based HDL diagramming tool☆87May 1, 2023Updated 3 years ago
- sample VCD files☆43Feb 13, 2026Updated 8 months ago
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- Value Change Dump (VCD) parser☆38Jan 9, 2026Updated 9 months ago
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 6 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- ☆12Jun 4, 2021Updated 5 years ago
- IOb_SoC version of the Picorv32 RISC-V Verilog IP core☆15Sep 21, 2026Updated 3 weeks ago
- vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.☆25Jan 7, 2016Updated 10 years ago
- Python Tool for UVM Testbench Generation☆57May 19, 2024Updated 2 years ago
- Hardware generator debugger☆79Feb 12, 2024Updated 2 years ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- WaveDrom compatible python command line☆117Jun 2, 2023Updated 3 years ago
- FuseSoc Verification Automation☆22Jul 21, 2022Updated 4 years ago
- wavedrom to verilog converter☆18Sep 14, 2021Updated 5 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Unit testing for cocotb☆177Sep 23, 2026Updated 2 weeks ago
- Python package for writing Value Change Dump (VCD) files.☆136Aug 11, 2026Updated 2 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆399Updated this week
- A simple function to add wavedrom diagrams into an ipython notebook.☆24Jan 14, 2022Updated 4 years ago
- A Python package to use FPGA development tools programmatically.☆151Sep 21, 2026Updated 3 weeks ago
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Updated this week
- Fixed point package for Python.☆37Apr 28, 2023Updated 3 years ago
- converts ValueChangeDump-Files (vcd) to tikz-timing-diagrams☆17Nov 19, 2021Updated 4 years ago
- This is an OOT module for GNU Radio integrating verilog simulation feature☆38Sep 23, 2019Updated 7 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics☆19Sep 13, 2023Updated 3 years ago
- A command-line tool for displaying vcd waveforms.☆72Feb 19, 2024Updated 2 years ago
- CLI for WaveDrom☆68Feb 22, 2024Updated 2 years ago
- Cross EDA Abstraction and Automation☆43Updated this week
- Create WaveJSON from VCD file. WaveDrom can convert it to timing diagram.☆43Jul 24, 2024Updated 2 years ago
- ☆12Dec 22, 2020Updated 5 years ago
- XC2064 bitstream documentation☆19Sep 24, 2018Updated 8 years ago
- Coarse Grained Reconfigurable Array Generator☆22Sep 16, 2026Updated 3 weeks ago
- Utilities for Avalon Memory Map☆11Jun 16, 2026Updated 3 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- 👾 Design ∪ Hardware☆79Sep 17, 2026Updated 3 weeks ago
- Mutation Cover with Yosys (MCY)☆100Sep 9, 2026Updated last month
- Device description files (architecture, timing, configuration bitstream, and general documentation) for EOS S3 MCU+eFPGA SoC☆27Sep 1, 2021Updated 5 years ago
- Generic Logic Interfacing Project☆49Jul 29, 2020Updated 6 years ago
- An abstraction library for interfacing EDA tools☆802Sep 15, 2026Updated 3 weeks ago
- hardware library for hwt (= ipcore repo)☆45Sep 20, 2026Updated 3 weeks ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆16Jan 22, 2025Updated last year