Alternatives and similar repositories for vcd2wavedrom:

Users that are interested in vcd2wavedrom are comparing it to the libraries listed below

• antmicro / cocotb-verilator-build
  ☆26Updated last year
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆58Updated this week
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆115Updated this week
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆33Updated 2 weeks ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆49Updated 6 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 6 months ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆53Updated last month
• cirosantilli / vcdvcd
  Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
  ☆57Updated 4 months ago
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆74Updated last week
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆57Updated this week
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆47Updated this week
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆110Updated 3 weeks ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆53Updated 5 years ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated 8 months ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆65Updated last month
• OSVVM / Documentation
  OSVVM Documentation
  ☆33Updated 2 weeks ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆33Updated 10 months ago
• stineje / sky130RHBDlib
  Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130
  ☆3Updated 3 months ago
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆66Updated 2 months ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆54Updated 4 years ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆50Updated 9 months ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆49Updated last year
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆65Updated 2 years ago
• tarik-ibrahimovic / eduBOS5
  A compact, configurable RISC-V core
  ☆11Updated last month
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆35Updated last month
• dmitrodem / p1735_decryptor
  IEEE P1735 decryptor for VHDL
  ☆30Updated 9 years ago
• nanamake / vcd2json
  Create WaveJSON from VCD file. WaveDrom can convert it to timing diagram.
  ☆35Updated 7 months ago
• antmicro / verilator-verification-features-tests
  ☆19Updated this week
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆37Updated 5 years ago
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆29Updated last week