Alternatives and similar repositories for vcd2wavedrom

Users that are interested in vcd2wavedrom are comparing it to the libraries listed below

• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆76Updated this week
• antmicro / cocotb-verilator-build
  ☆26Updated 2 years ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 10 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 4 months ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆72Updated last year
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆58Updated 2 weeks ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆69Updated 2 months ago
• themperek / spicebind
  SpiceBind – spice inside HDL simulator
  ☆56Updated 5 months ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆52Updated 2 years ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆128Updated 6 months ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆62Updated 3 weeks ago
• tsfpga / tsfpga
  A flexible and scalable development platform for modern FPGA projects.
  ☆38Updated last week
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆51Updated this week
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆73Updated 2 weeks ago
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆80Updated 2 weeks ago
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆58Updated last month
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆124Updated last year
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆155Updated this week
• cirosantilli / vcdvcd
  Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
  ☆65Updated last month
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 7 months ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆64Updated 4 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆48Updated last year
• olofk / ipyxact
  Python-based IP-XACT parser
  ☆142Updated last year
• pieter3d / simview
  ☆88Updated last month
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆48Updated 3 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆149Updated 6 months ago
• Nic30 / pyDigitalWaveTools
  Python library for operations with VCD and other digital wave files
  ☆53Updated 3 weeks ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆55Updated last year
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year