Dinistro / circt-stream
A stream to RTL compiler based on MLIR and CIRCT
☆15Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for circt-stream
- HeteroCL-MLIR dialect for accelerator design☆40Updated 2 months ago
- A hardware synthesis framework with multi-level paradigm☆37Updated last year
- CGRA framework with vectorization support.☆19Updated this week
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆44Updated last year
- An LLVM pass to prove that an II works for the given loop for Vitis HLS☆11Updated 3 years ago
- A hardware design framework with a timing-deterministic, Rust-embedded HDL and the compilation flow.☆12Updated 8 months ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆36Updated this week
- A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https:/…☆19Updated last year
- Polyhedral High-Level Synthesis in MLIR☆29Updated last year
- ☆21Updated last month
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆53Updated last month
- ☆36Updated 7 months ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆94Updated 7 months ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- Intel Compiler for SystemC☆23Updated last year
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆19Updated this week
- ☆26Updated 7 years ago
- SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.☆11Updated 4 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆56Updated this week
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆19Updated this week
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 3 years ago
- A polyhedral compiler for hardware accelerators☆56Updated 3 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆47Updated 4 years ago
- ☆13Updated last year
- 📥 🎯 (1,4/4) an MLIR-based toolchain with Vitis HLS LLVM input/output targeting FPGAs.☆13Updated 2 years ago
- ☆33Updated 3 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆23Updated 4 years ago
- ☆15Updated 2 months ago
- Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)☆29Updated 6 months ago
- Papers, Posters, Presentations, Documentation...☆18Updated 10 months ago