pulp-platform / DeeployLinks
DNN Compiler for Heterogeneous SoCs
☆44Updated last week
Alternatives and similar repositories for Deeploy
Users that are interested in Deeploy are comparing it to the libraries listed below
Sorting:
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆157Updated this week
- ☆47Updated 4 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆58Updated last month
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆86Updated 3 months ago
- ☆32Updated 3 months ago
- matrix-coprocessor for RISC-V☆19Updated 4 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆58Updated last week
- ☆63Updated 3 months ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆31Updated 11 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- PyTorch model to RTL flow for low latency inference☆131Updated last year
- Machine-Learning Accelerator System Exploration Tools☆173Updated 2 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆57Updated 10 months ago
- A DSL for Systolic Arrays☆80Updated 6 years ago
- An Open-Source Tool for CGRA Accelerators☆67Updated 4 months ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆150Updated this week
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆74Updated last week
- Floating-Point Optimized On-Device Learning Library for the PULP Platform.☆36Updated this week
- ☆72Updated 2 weeks ago
- Topics in Machine Learning Accelerator Design☆84Updated 2 years ago
- NeuraLUT-Assemble☆38Updated last week
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆136Updated 2 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆60Updated 10 months ago
- eyeriss-chisel3☆41Updated 3 years ago
- muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.☆85Updated last week
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆62Updated 5 months ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆40Updated 2 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 6 months ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated 11 months ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆39Updated this week