pulp-platform / Deeploy
ONNX-to-C Compiler for Heterogeneous SoCs
☆15Updated last week
Related projects ⓘ
Alternatives and complementary repositories for Deeploy
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆113Updated last week
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆23Updated 7 months ago
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆20Updated last year
- ☆26Updated 5 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆83Updated 4 years ago
- ☆37Updated 5 years ago
- An Open-Source Tool for CGRA Accelerators☆57Updated 3 months ago
- ☆3Updated 3 years ago
- eyeriss-chisel3☆39Updated 2 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆47Updated 4 years ago
- A verilog implementation for Network-on-Chip☆67Updated 6 years ago
- ☆87Updated 8 months ago
- This is a verilog implementation of 4x4 systolic array multiplier☆39Updated 4 years ago
- A Fast, Low-Overhead On-chip Network☆138Updated this week
- A DSL for Systolic Arrays☆78Updated 5 years ago
- ☆60Updated 5 years ago
- IC implementation of TPU☆86Updated 4 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆129Updated 4 years ago
- ☆37Updated 4 months ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆59Updated 11 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆40Updated this week
- Vector processor for RISC-V vector ISA☆110Updated 4 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆65Updated 3 years ago
- ☆12Updated this week
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆71Updated 3 months ago
- RTL implementation of Flex-DPE.☆91Updated 4 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆60Updated this week
- ☆38Updated 2 months ago
- HLS for Networks-on-Chip☆31Updated 3 years ago
- An integrated CGRA design framework☆83Updated last week