DNN Compiler for Heterogeneous SoCs
☆69Jun 2, 2026Updated last week
Alternatives and similar repositories for Deeploy
Users that are interested in Deeploy are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆41Mar 5, 2024Updated 2 years ago
- A reliable, real-time subsystem for the Carfield SoC☆20Dec 2, 2025Updated 6 months ago
- ☆33Mar 12, 2026Updated 2 months ago
- ☆72Apr 22, 2025Updated last year
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆193Apr 27, 2026Updated last month
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- matrix-coprocessor for RISC-V☆32Feb 27, 2026Updated 3 months ago
- ☆39Updated this week
- ☆95Oct 18, 2023Updated 2 years ago
- Welcome to the official repository of AC-LORA: (Almost) Training-Free Access Control-Aware Multi-Modal LLMs, a mechanism that provides tr…☆21Nov 14, 2025Updated 6 months ago
- whatever it means☆16May 19, 2026Updated 3 weeks ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆32May 20, 2026Updated 2 weeks ago
- A reference implementation of the Mind Mappings Framework.☆30Dec 2, 2021Updated 4 years ago
- A high-efficiency system-on-chip for floating-point compute workloads.☆48Jan 13, 2025Updated last year
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆21Oct 22, 2025Updated 7 months ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- NEural Minimizer for pytOrch☆47Jul 25, 2024Updated last year
- A lightweight memory allocator for hardware-accelerated machine learning☆188Apr 6, 2026Updated 2 months ago
- RISC-V ISA based 32-bit processor written in HLS☆16Nov 7, 2019Updated 6 years ago
- Tool for the deployment and analysis of TinyML applications on TFLM and MicroTVM backends☆34May 20, 2026Updated 2 weeks ago
- NeuroSpector: Dataflow and Mapping Optimizer for Deep Neural Network Accelerators☆23Mar 20, 2025Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆56Feb 6, 2020Updated 6 years ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆230Nov 22, 2023Updated 2 years ago
- LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust☆39May 17, 2024Updated 2 years ago
- ☆24Apr 17, 2026Updated last month
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.☆319May 20, 2026Updated 2 weeks ago
- IREE compiler and runtime for Snitch☆15May 14, 2026Updated 3 weeks ago
- Input / Output Physical Memory Protection Unit for RISC-V☆15Jul 20, 2023Updated 2 years ago
- GPU CRF-CTC decoding for nanopore basecalling☆15Jun 1, 2026Updated last week
- CV32E40X Design-Verification environment☆16Jun 2, 2026Updated last week
- Tool for optimize CNN blocking☆95Mar 22, 2020Updated 6 years ago
- ☆62Mar 31, 2025Updated last year
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆86Apr 26, 2026Updated last month
- A dependency management tool for hardware projects.☆374Jun 2, 2026Updated last week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Atom Hardware IDE☆13May 4, 2021Updated 5 years ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆20May 29, 2026Updated last week
- A public repository discussing the PULP (Parallel Ultra Low Power) platform for open-source RISC-V processors and associated software.☆31Nov 18, 2025Updated 6 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆69Jul 5, 2025Updated 11 months ago
- Automatic SystemVerilog linting in github actions with the help of Verible☆37Oct 23, 2024Updated last year
- Control Logic Synthesis: Drawing the Rest of the OWL☆13Jun 17, 2024Updated last year
- ☆15May 29, 2026Updated last week