IPADS-SAI / WaferAI-SIMLinks
The wafer-native AI accelerator simulation platform and inference engine.
☆23Updated this week
Alternatives and similar repositories for WaferAI-SIM
Users that are interested in WaferAI-SIM are comparing it to the libraries listed below
Sorting:
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆81Updated 8 months ago
- Domain-Specific Architecture Generator 2☆21Updated 3 years ago
- HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs☆39Updated last year
- GPGPU-Sim 中文注释版代码,包含 GPGPU-Sim 模拟器的最新版代码,经过中文注释,以帮助中文用户更好地理解和使用该模拟器。☆28Updated last year
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆45Updated 2 years ago
- ☆52Updated last month
- Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"☆31Updated last year
- PIM-DL: Expanding the Applicability of Commodity DRAM-PIMs for Deep Learning via Algorithm-System Co-Optimization☆34Updated last year
- ☆26Updated 10 months ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆67Updated last week
- ☆29Updated 2 months ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆107Updated 8 months ago
- Artifact material for [HPCA 2025] #2108 "UniNDP: A Unified Compilation and Simulation Tool for Near DRAM Processing Architectures"☆51Updated 4 months ago
- STONNE Simulator integrated into SST Simulator☆22Updated last year
- Artifact for paper "PIM is All You Need: A CXL-Enabled GPU-Free System for LLM Inference", ASPLOS 2025☆117Updated 8 months ago
- WaferLLM: Large Language Model Inference at Wafer Scale☆79Updated 2 months ago
- Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…☆22Updated 9 months ago
- Artifact for "DX100: A Programmable Data Access Accelerator for Indirection (ISCA 2025)" paper☆16Updated last month
- ☆28Updated 2 years ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆33Updated last year
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆45Updated last year
- EDA toolchain for processing-in-memory architectures, including an architecture synthesizer, a compiler, and a simulator☆14Updated 6 months ago
- A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0☆51Updated 5 months ago
- ☆35Updated 6 months ago
- ☆53Updated 7 months ago
- MICRO22 artifact evaluation for Sparseloop☆46Updated 3 years ago
- Serpens is an HBM FPGA accelerator for SpMV☆22Updated last year
- ☆29Updated 4 years ago
- SimplePIM is the first high-level programming framework for real-world processing-in-memory (PIM) architectures. Described in the PACT 20…☆31Updated 2 years ago
- NeuPIMs: NPU-PIM Heterogeneous Acceleration for Batched LLM Inferencing☆108Updated last year