KULeuven-MICAS / DeFiNESLinks
A framework for fast exploration of the depth-first scheduling space for DNN accelerators
☆43Updated 2 years ago
Alternatives and similar repositories for DeFiNES
Users that are interested in DeFiNES are comparing it to the libraries listed below
Sorting:
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆74Updated 2 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 6 months ago
- ☆48Updated 4 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆55Updated 2 years ago
- A co-design architecture on sparse attention☆55Updated 4 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆62Updated 3 months ago
- RTL implementation of Flex-DPE.☆115Updated 5 years ago
- MICRO22 artifact evaluation for Sparseloop☆46Updated 3 years ago
- Open-source of MSD framework☆16Updated 2 years ago
- Eyeriss chip simulator☆39Updated 5 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆50Updated 10 months ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆82Updated 10 months ago
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆175Updated 2 months ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆71Updated 3 months ago
- ☆58Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆83Updated 4 years ago
- ☆32Updated 9 months ago
- ☆35Updated 5 years ago
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆154Updated 7 months ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆46Updated last year
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆96Updated 4 years ago
- ☆73Updated 11 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Updated last year
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆107Updated 8 months ago
- ☆19Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 4 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆60Updated 4 years ago
- STONNE: A Simulation Tool for Neural Networks Engines☆146Updated 7 months ago
- Tool for optimize CNN blocking☆94Updated 5 years ago