KULeuven-MICAS / DeFiNES
A framework for fast exploration of the depth-first scheduling space for DNN accelerators
☆38Updated 2 years ago
Alternatives and similar repositories for DeFiNES:
Users that are interested in DeFiNES are comparing it to the libraries listed below
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆51Updated last week
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆49Updated last month
- A co-design architecture on sparse attention☆52Updated 3 years ago
- MICRO22 artifact evaluation for Sparseloop☆43Updated 2 years ago
- ☆45Updated 3 years ago
- ☆26Updated last month
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆40Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆76Updated 3 years ago
- Open-source of MSD framework☆16Updated last year
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆52Updated 2 weeks ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆67Updated last month
- RTL implementation of Flex-DPE.☆99Updated 5 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆51Updated last month
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆26Updated last year
- ☆39Updated 10 months ago
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆145Updated last month
- ☆25Updated 9 months ago
- ☆34Updated 4 years ago
- Implementation of Microscaling data formats in SystemVerilog.☆17Updated 8 months ago
- [FPGA 2024]FPGA Accelerator for Imbalanced SpMV using HLS☆12Updated 2 months ago
- ☆43Updated 2 years ago
- ☆33Updated 3 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆79Updated 9 months ago
- Eyeriss chip simulator☆36Updated 5 years ago
- ☆33Updated 6 years ago
- ☆50Updated last year
- The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware …☆129Updated last year
- Model LLM inference on single-core dataflow accelerators☆10Updated 2 months ago
- A bit-level sparsity-awared multiply-accumulate process element.☆15Updated 9 months ago
- A reference implementation of the Mind Mappings Framework.☆29Updated 3 years ago