KULeuven-MICAS / zigzag-llmLinks
Model LLM inference on single-core dataflow accelerators
☆16Updated this week
Alternatives and similar repositories for zigzag-llm
Users that are interested in zigzag-llm are comparing it to the libraries listed below
Sorting:
- A bit-level sparsity-awared multiply-accumulate process element.☆18Updated last year
- Open-source of MSD framework☆16Updated 2 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆71Updated last month
- A co-design architecture on sparse attention☆54Updated 4 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆54Updated 2 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 5 months ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆42Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆83Updated 4 years ago
- bitfusion verilog implementation☆12Updated 3 years ago
- ☆47Updated 4 years ago
- MICRO22 artifact evaluation for Sparseloop☆44Updated 3 years ago
- RTL implementation of Flex-DPE.☆115Updated 5 years ago
- ☆20Updated last year
- Collection of kernel accelerators optimised for LLM execution☆25Updated 3 weeks ago
- An FPGA Accelerator for Transformer Inference☆92Updated 3 years ago
- ☆18Updated last year
- C++ code for HLS FPGA implementation of transformer☆18Updated last year
- ☆19Updated 6 months ago
- Implementation of Microscaling data formats in SystemVerilog.☆28Updated 5 months ago
- ☆35Updated 5 years ago
- ☆18Updated 2 years ago
- ☆74Updated 2 months ago
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆169Updated last month
- Accelerate multihead attention transformer model using HLS for FPGA☆12Updated 2 years ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆45Updated last year
- Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…☆21Updated 8 months ago
- ☆46Updated 2 years ago
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆77Updated 7 months ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆30Updated last year
- A reading list for SRAM-based Compute-In-Memory (CIM) research.☆103Updated last month