KULeuven-MICAS / zigzag-imc
HW accelerator mapping optimization framework for in-memory computing
☆22Updated 3 months ago
Alternatives and similar repositories for zigzag-imc:
Users that are interested in zigzag-imc are comparing it to the libraries listed below
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆51Updated 2 months ago
- MICRO22 artifact evaluation for Sparseloop☆43Updated 2 years ago
- ☆26Updated last year
- ☆39Updated 9 months ago
- A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0☆13Updated 2 months ago
- Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration☆22Updated 3 years ago
- ☆16Updated 2 years ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆30Updated 11 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆74Updated 3 years ago
- ☆26Updated 5 months ago
- ☆33Updated 3 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆52Updated last week
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆34Updated 2 years ago
- A comprehensive tool that allows for system-level performance estimation of chiplet-based In-Memory computing (IMC) architectures.☆21Updated 9 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆49Updated last month
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆38Updated 2 years ago
- A reference implementation of the Mind Mappings Framework.☆29Updated 3 years ago
- ☆71Updated 2 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆48Updated 3 years ago
- Neural Network Evaluation Tool on Crossbar-based Accelerator with Resistive Memory☆40Updated 5 years ago
- ☆9Updated last year
- ☆10Updated 2 years ago
- A general framework for optimizing DNN dataflow on systolic array☆34Updated 4 years ago
- ☆34Updated 4 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆79Updated last year
- An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization☆21Updated 5 months ago
- A Fast DNN Accelerator Design Space Exploration Framework.☆46Updated 2 years ago
- ☆16Updated 2 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆63Updated 2 years ago