IObundle / iob-versatLinks
Coarse Grained Reconfigurable Array
☆20Updated last month
Alternatives and similar repositories for iob-versat
Users that are interested in iob-versat are comparing it to the libraries listed below
Sorting:
- ☆29Updated 6 years ago
- Project repo for the POSH on-chip network generator☆52Updated 10 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆98Updated this week
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Updated 12 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆76Updated 6 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 4 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆98Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- ☆74Updated 5 years ago
- ☆82Updated 11 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆75Updated 10 years ago
- DUTH RISC-V Microprocessor☆23Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆109Updated 4 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Updated 3 years ago
- HLS for Networks-on-Chip☆39Updated 4 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆34Updated 2 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆55Updated 6 years ago
- BlackParrot on Zynq☆48Updated this week
- Platform Level Interrupt Controller☆44Updated last year
- pulp_soc is the core building component of PULP based SoCs☆82Updated 11 months ago
- SystemVerilog modules and classes commonly used for verification☆57Updated last month
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 3 months ago
- ☆114Updated 3 months ago
- openHMC - an open source Hybrid Memory Cube Controller☆50Updated 9 years ago
- Modular Multi-ported SRAM-based Memory☆31Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆20Updated this week
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Updated 3 weeks ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Updated 5 years ago
- ☆31Updated 5 years ago