Alternatives and similar repositories for py2hwsw

Users that are interested in py2hwsw are comparing it to the libraries listed below

• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆52Updated last week
• wyvernSemi / mem_model
  High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
  ☆25Updated 5 months ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 7 months ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆43Updated last year
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆61Updated 2 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 5 months ago
• aignacio / nox
  RISC-V Nox core
  ☆71Updated 5 months ago
• wyvernSemi / vproc
  Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
  ☆69Updated 3 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆44Updated 2 years ago
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆93Updated last year
• AsFigo / apb_uvc_verilator
  APB UVC ported to Verilator
  ☆11Updated 2 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 6 months ago
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆45Updated last week
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆120Updated 2 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆51Updated 8 months ago
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated 2 months ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆30Updated last year
• munetomo-maruyama / mmRISC-1
  RISC-V RV32IMAFC Core for MCU
  ☆40Updated 10 months ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆71Updated 6 months ago
• mciepluc / apbi2c_cocotb_example
  An example Python-based MDV testbench for apbi2c core
  ☆31Updated last year
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆73Updated last year
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆43Updated last week
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆54Updated 3 years ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆41Updated last month
• antmicro / cocotb-verilator-build
  ☆26Updated 2 years ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆43Updated 2 years ago
• themperek / spicebind
  SpiceBind – spice inside HDL simulator
  ☆56Updated 5 months ago
• PeterMonsson / sv_waveterm
  ☆10Updated 2 years ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆86Updated 5 years ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆77Updated 3 years ago