IObundle / py2hwsw
a Python framework for managing embedded HW/SW projects
☆16Updated this week
Alternatives and similar repositories for py2hwsw:
Users that are interested in py2hwsw are comparing it to the libraries listed below
- Running Linux on IOb-SoC-OpenCryptoHW☆14Updated 8 months ago
- Platform Level Interrupt Controller☆40Updated last year
- SystemVerilog Functional Coverage for RISC-V ISA☆28Updated 7 months ago
- YosysHQ SVA AXI Properties☆37Updated 2 years ago
- APB UVC ported to Verilator☆11Updated last year
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆41Updated 2 years ago
- Basic Verilog Ethernet core and C driver functions☆11Updated 2 months ago
- Coarse Grained Reconfigurable Array☆19Updated 3 months ago
- Hamming ECC Encoder and Decoder to protect memories☆32Updated 3 months ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated last year
- SystemVerilog Linter based on pyslang☆30Updated this week
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆29Updated last week
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆23Updated 5 months ago
- ☆20Updated 5 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 6 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆45Updated 6 months ago
- Reconfigurable Hardware-Accelerated Open-Source Cryptographic IP Cores☆11Updated 2 months ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- An automatic clock gating utility☆47Updated 3 weeks ago
- Python interface for cross-calling with HDL☆32Updated last month
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- RISC-V Nox core☆62Updated last month
- IOb_SoC version of the Picorv32 RISC-V Verilog IP core☆13Updated last month
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆54Updated 3 months ago
- Andes Vector Extension support added to riscv-dv☆15Updated 4 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆38Updated 4 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆32Updated this week
- Making cocotb testbenches that bit easier☆29Updated last month