IObundle / py2hwsw

Related projects ⓘ

Alternatives and complementary repositories for py2hwsw

• IObundle / iob-soc-opencryptolinux
  Running Linux on IOb-SoC-OpenCryptoHW
  ☆13Updated 3 months ago
• IObundle / iob-soc-opencryptohw
  Reconfigurable Hardware-Accelerated Open-Source Cryptographic IP Cores
  ☆11Updated 3 months ago
• blockwork-eda / blockwork
  An opinionated build environment for EDA projects
  ☆15Updated this week
• OS-EDA / Course
  Home of the open-source EDA course.
  ☆15Updated last week
• AsFigo / apb_uvc_verilator
  APB UVC ported to Verilator
  ☆11Updated last year
• edaa-org / pyEDAA.Reports
  Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.
  ☆15Updated last week
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆48Updated 6 months ago
• IObundle / iob-picorv32
  IOb_SoC version of the Picorv32 RISC-V Verilog IP core
  ☆13Updated 3 months ago
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆44Updated 4 months ago
• pulp-platform / axi_mem_if
  Simple single-port AXI memory interface
  ☆36Updated 5 months ago
• IObundle / iob-versat
  Coarse Grained Reconfigurable Array
  ☆19Updated 3 months ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆44Updated 6 months ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆153Updated last week
• efabless / foss-asic-tools
  FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already ins…
  ☆73Updated 3 months ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆53Updated 4 months ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆59Updated last month
• IUST-Computer-Organization / LUMOS
  Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor
  ☆48Updated 4 months ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆105Updated 2 months ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆35Updated 6 months ago
• hanysalah / Design-Pattern-in-SV
  This repo is created to include illustrative examples on object oriented design pattern in SV
  ☆55Updated last year
• verilator / verilator-announce
  Announcements related to Verilator
  ☆38Updated 4 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆146Updated this week
• AmeerAbdelhadi / 2D-Binary-Content-Addressable-Memory-BCAM
  Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)
  ☆19Updated last week
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆99Updated 2 weeks ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆98Updated 3 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆58Updated 4 years ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆56Updated 3 years ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆31Updated this week
• shariethernet / RPHAX
  RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…
  ☆16Updated last year
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆36Updated this week