IObundle / py2hwsw
a Python framework for managing embedded HW/SW projects
☆14Updated this week
Alternatives and similar repositories for py2hwsw:
Users that are interested in py2hwsw are comparing it to the libraries listed below
- Running Linux on IOb-SoC-OpenCryptoHW☆14Updated 7 months ago
- Platform Level Interrupt Controller☆37Updated 10 months ago
- SystemVerilog Functional Coverage for RISC-V ISA☆25Updated 5 months ago
- APB UVC ported to Verilator☆11Updated last year
- ☆36Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆30Updated 5 months ago
- An automatic clock gating utility☆45Updated 8 months ago
- A simple DDR3 memory controller☆54Updated 2 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆65Updated 6 months ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 4 years ago
- RISC-V Nox core☆62Updated 7 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆40Updated last year
- ☆59Updated 3 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆45Updated 5 months ago
- YosysHQ SVA AXI Properties☆37Updated 2 years ago
- ☆31Updated 2 months ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- Open FPGA Modules☆23Updated 5 months ago
- Coarse Grained Reconfigurable Array☆19Updated last month
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 10 months ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆28Updated last month
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated 10 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 10 months ago
- SystemVerilog frontend for Yosys☆80Updated this week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆68Updated last week
- Characterizer☆21Updated 7 months ago
- RISC-V RV32IMAFC Core for MCU☆36Updated last month
- Open source ISS and logic RISC-V 32 bit project☆43Updated 3 months ago
- ☆41Updated 5 years ago
- This repository is compilation of basics of System Verilog Assertions in context of formal verification☆20Updated 6 years ago