IObundle / iob-picorv32
IOb_SoC version of the Picorv32 RISC-V Verilog IP core
☆13Updated last month
Alternatives and similar repositories for iob-picorv32:
Users that are interested in iob-picorv32 are comparing it to the libraries listed below
- a Python framework for managing embedded HW/SW projects☆16Updated this week
- Running Linux on IOb-SoC-OpenCryptoHW☆14Updated 8 months ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆29Updated last week
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆54Updated 3 months ago
- Reconfigurable Binary Engine☆16Updated 4 years ago
- APB UVC ported to Verilator☆11Updated last year
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 8 years ago
- Simple single-port AXI memory interface☆41Updated 11 months ago
- JTAG Test Access Port (TAP)☆33Updated 10 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆41Updated 2 years ago
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- RISC-V soft-core PEs for TaPaSCo☆18Updated 10 months ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 5 years ago
- ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set☆6Updated 2 years ago
- Hamming ECC Encoder and Decoder to protect memories☆32Updated 3 months ago
- ☆38Updated last year
- ☆20Updated 5 years ago
- Reconfigurable Hardware-Accelerated Open-Source Cryptographic IP Cores☆11Updated 2 months ago
- Platform Level Interrupt Controller☆40Updated last year
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆31Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 2 months ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆31Updated 4 months ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated last year
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆34Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago
- ☆27Updated 3 weeks ago
- Coarse Grained Reconfigurable Array☆19Updated 3 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆45Updated 6 months ago
- SystemVerilog Functional Coverage for RISC-V ISA☆28Updated 7 months ago